component
4N65L
Public Made by Adomby adom
UMW MOSFETs, TO-252. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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4N65L
UMW · MOSFETs · TO-252
4N65L from UMW, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | GATE terminal of the 650V N-channel MOSFET; the absolute maximum gate-source voltage is VGS = ±30 V. |
| 2 | D | passive | DRAIN terminal of the MOSFET; rated VDS 650 V with continuous drain current ID 4 A at TC=25°C (2.5 A at TC=100°C). |
| 3 | S | passive | SOURCE terminal of the MOSFET, the reference terminal for the gate-source voltage rating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source Breakdown Voltage | BVDSS | 650 | V | VGS=0V, ID=250µA | 3 | ||
| Gate Threshold Voltage | VGS(th) | 2 | 4 | V | VDS=VGS, ID=250µA | 3 | |
| Gate-body Leakage Current | IGSS | -100 | 100 | nA | VGS=±30V | 3 | |
| Drain-source Leakage Current | IDSS | 1 | µA | VDS=650V, VGS=0V, TJ=25°C | 3 | ||
| Drain-source Leakage Current | IDSS | 10 | µA | VDS=520V, VGS=0V, TJ=125°C | 3 | ||
| Static Drain-source On Resistance | RDS(ON) | 2.7 | Ω | VGS=10V, ID=2A | 3 | ||
| Drain-source Voltage | VDS | 650 | V | TC=25°C | 1 | ||
| Gate-source Voltage | VGS | -30 | 30 | V | 1 | ||
| Continuous Drain Current | ID | 4 | A | TC=25°C | 1 | ||
| Continuous Drain Current | ID | 2.5 | A | TC=100°C | 1 | ||
| Drain Current - Pulsed | IDM | 16 | A | Pulse width limited by maximum junction temperature (note ①) | 1 | ||
| Junction Temperature | TJ | 150 | °C | 1 | |||
| Storage Temperature | TSTG | -55 | 150 | °C | 1 | ||
| Single Pulse Avalanche Energy | EAS | 128 | mJ | Starting TJ=25°C, VDD=50V, L=25mH, RG=25Ω, IAS=4A (note ②) | 1 |
CAD (KiCad official)
- Symbol:
4N65L - Footprint:
Package_TO_SOT_SMD:TO-252-2 - 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files:
4n65l-etched.step/4n65l-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);4n65l.step/4n65l.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (11 pp, sha256
e312ff44cb169132, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 4N65L
**UMW** · MOSFETs · TO-252
4N65L from UMW, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | GATE terminal of the 650V N-channel MOSFET; the absolute maximum gate-source voltage is VGS = ±30 V. |
| 2 | D | passive | DRAIN terminal of the MOSFET; rated VDS 650 V with continuous drain current ID 4 A at TC=25°C (2.5 A at TC=100°C). |
| 3 | S | passive | SOURCE terminal of the MOSFET, the reference terminal for the gate-source voltage rating. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source Breakdown Voltage | BVDSS | 650 | | | V | VGS=0V, ID=250µA | 3 |
| Gate Threshold Voltage | VGS(th) | 2 | | 4 | V | VDS=VGS, ID=250µA | 3 |
| Gate-body Leakage Current | IGSS | -100 | | 100 | nA | VGS=±30V | 3 |
| Drain-source Leakage Current | IDSS | | | 1 | µA | VDS=650V, VGS=0V, TJ=25°C | 3 |
| Drain-source Leakage Current | IDSS | | | 10 | µA | VDS=520V, VGS=0V, TJ=125°C | 3 |
| Static Drain-source On Resistance | RDS(ON) | | | 2.7 | Ω | VGS=10V, ID=2A | 3 |
| Drain-source Voltage | VDS | | | 650 | V | TC=25°C | 1 |
| Gate-source Voltage | VGS | -30 | | 30 | V | | 1 |
| Continuous Drain Current | ID | | | 4 | A | TC=25°C | 1 |
| Continuous Drain Current | ID | | | 2.5 | A | TC=100°C | 1 |
| Drain Current - Pulsed | IDM | | | 16 | A | Pulse width limited by maximum junction temperature (note ①) | 1 |
| Junction Temperature | TJ | | | 150 | °C | | 1 |
| Storage Temperature | TSTG | -55 | | 150 | °C | | 1 |
| Single Pulse Avalanche Energy | EAS | | | 128 | mJ | Starting TJ=25°C, VDD=50V, L=25mH, RG=25Ω, IAS=4A (note ②) | 1 |
## CAD (KiCad official)
- Symbol: `4N65L`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files: `4n65l-etched.step` / `4n65l-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `4n65l.step` / `4n65l.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8763509784945266688) (11 pp, sha256 `e312ff44cb169132`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/4n65l-datasheet.pdf)