# 4N50L

**UMW** · MOSFETs · TO-252

4N50L from UMW, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limited to ±30 V (VGSS), threshold VGS(th) 2.0 to 4.0 V at ID=0.25 mA. |
| 2 | D | passive | Drain; drain-source voltage up to 500 V (VDSS) and continuous current 5 A at TC=25°C (pulsed 15 A), also connected to the exposed tab. |
| 3 | S | passive | Source; connected to the body diode with continuous diode forward current IS of 5 A (pulsed 15 A). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | TO-252 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 500 | V |  | 1 |
| Continuous drain current | ID |  |  | 5 | A | TC = 25°C | 1 |
| Continuous drain current | ID |  |  | 2.5 | A | TC = 100°C | 1 |
| Pulsed drain current | IDM |  |  | 15 | A |  | 1 |
| Gate-Source voltage | VGSS | -30 |  | 30 | V |  | 1 |
| Avalanche energy, single pulse | EAS |  |  | 106 | mJ |  | 1 |
| Power Dissipation | PD |  |  | 76 | W |  | 1 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 1 |
| Continuous diode forward current | IS |  |  | 5 | A |  | 1 |
| Diode pulse current | IS,pulse |  |  | 15 | A |  | 1 |
| Soldering temperature, wave soldering at leads only | Tsold |  |  | 260 | °C | 1.6mm from case for 10s | 1 |
| Thermal Resistance, Junction-to-Case | RθJC |  | 1.65 |  | °C/W |  | 1 |
| Thermal Resistance, Junction-to-Ambient, minimal footprint | RθJA |  | 62 |  | °C/W | minimal footprint (note 4) | 1 |
| Drain-source breakdown voltage | BVDSS | 500 |  |  | V | VGS=0V, ID=0.25mA | 2 |
| Gate threshold voltage | VGS(th) | 2 |  | 4 | V | VDS=VGS, ID=0.25mA | 2 |
| Drain cut-off current | IDSS |  |  | 1 | μA | VDS=500V, VGS=0 V, Tj = 25°C | 2 |
| Gate leakage current, Forward | IGSSF |  |  | 100 | nA | VGS=30V, VDS=0V | 2 |
| Gate leakage current, Reverse | IGSSR |  |  | -100 | nA | VGS=-30V, VDS=0V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 2.05 | 2.4 | Ω | VGS=10 V, ID=2A | 2 |
| Diode forward voltage | VSD |  |  | 1.3 | V | VGS=0V, IF=7A | 2 |

## CAD (KiCad official)

- Symbol: `4N50L`
- Footprint: `Package_TO_SOT_SMD:TO-252-2`
- 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files: `4n50l-etched.step` / `4n50l-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `4n50l.step` / `4n50l.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604424769014018048) (6 pp, sha256 `491f1706e03804bf`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/4n50l-datasheet.pdf)