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Ray Publish 0.1.0 0729835 20d ago

4882

HL · MOSFETs · SOP-8

4882 from HL, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel, 40V VDS, 8A continuous drain current at TA=25°C).
2 G1 input Gate of MOSFET 1; maximum gate-source voltage is ±20V.
3 S2 passive Source of MOSFET 2 (N-channel, 40V VDS, 8A continuous drain current at TA=25°C).
4 G2 input Gate of MOSFET 2; maximum gate-source voltage is ±20V.
5 D2 passive Drain of MOSFET 2; maximum drain-source voltage is 40V.
6 D2 passive Drain of MOSFET 2, internally tied to the other D2 pin; maximum drain-source voltage is 40V.
7 D1 passive Drain of MOSFET 1, internally tied to the other D1 pin; maximum drain-source voltage is 40V.
8 D1 passive Drain of MOSFET 1; maximum drain-source voltage is 40V.

Key specifications

Parameter Value
Manufacturer HL
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: 4882
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: 4882-etched.step / 4882-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 4882.step / 4882.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HL datasheet (5 pp, sha256 35906e1155d562dd, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF