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4805

HL · MOSFETs · SOP-8

4805 from HL, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of channel 1 of this dual P-channel MOSFET; device rated VDS -30 V and continuous ID -9.5 A at Ta = 25 °C.
2 G1 input Gate of channel 1; gate-source voltage limited to ±20 V.
3 S2 passive Source of channel 2 of this dual P-channel MOSFET; device rated VDS -30 V and continuous ID -9.5 A at Ta = 25 °C.
4 G2 input Gate of channel 2; gate-source voltage limited to ±20 V.
5 D2 passive Drain of channel 2; pins 5 and 6 are both internally D2, device rated VDS -30 V.
6 D2 passive Drain of channel 2; pins 5 and 6 are both internally D2, device rated VDS -30 V.
7 D1 passive Drain of channel 1; pins 7 and 8 are both internally D1, device rated VDS -30 V.
8 D1 passive Drain of channel 1; pins 7 and 8 are both internally D1, device rated VDS -30 V.

Key specifications

Parameter Value
Manufacturer HL
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: 4805
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: 4805-etched.step / 4805-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 4805.step / 4805.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HL datasheet (6 pp, sha256 041a58b64dd9d5d7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF