component
2SK1764-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, SOT-89. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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2SK1764-VB
VBsemi Elec · MOSFETs · SOT-89
2SK1764-VB from VBsemi Elec, in a SOT-89. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limit is ±20 V, and threshold voltage is 1.5 V at ID = 250 µA. |
| 2 | D | passive | Drain, connected to the exposed tab; the drain-source voltage is 60 V maximum. |
| 3 | S | passive | Source; the continuous source-drain diode current is 5.2 A at TC = 25 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SOT-89 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Drain-Source Voltage | VDS | 60 | V | 1 | |||
| Maximum Power Dissipation | PD | 2.5 | W | TA = 25 °C, note c | 1 | ||
| Maximum Power Dissipation | PD | 1.6 | W | TA = 70 °C, note c | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Soldering Recommendations (Peak Temperature) | 260 | °C | Peak temperature, notes e, f | 1 | |||
| Maximum Junction-to-Ambient | RthJA | 40 | 50 | °C/W | t ≤ 5 s | 1 | |
| Maximum Junction-to-Ambient | RthJA | 95 | °C/W | Steady State, note d | 1 | ||
| Maximum Junction-to-Foot (Drain) | RthJF | 15 | 20 | °C/W | Steady State | 1 | |
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ±12 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 60 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 10 | µA | VDS = 60 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.076 | Ω | VGS = 10 V, ID = 4.5 A | 2 | ||
| Total Gate Charge | Qg | 22 | 33 | nC | VDS = 10 V, VGS = 10 V, ID = 6.3 A | 2 | |
| Total Gate Charge | Qg | 10 | 15 | nC | VDS = 10 V, VGS = 4.5 V, ID = 6.3 A | 2 | |
| Turn-on Delay Time | td(on) | 15 | 25 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 35 | 55 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 | |
| Fall Time | tf | 12 | 20 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 | |
| Turn-on Delay Time | td(on) | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 12 | 20 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 25 | 40 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Fall Time | tf | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Body Diode Voltage | VSD | 0.8 | 1.2 | V | IS = 6.7 A, VGS = 0 V | 2 | |
| Body Diode Reverse Recovery Time | trr | 20 | 40 | ns | IF = 6.7 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 | |
| Body Diode Reverse Recovery Charge | Qrr | 10 | 20 | nC | IF = 6.7 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | e. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result | 1 |
CAD (KiCad official)
- Symbol:
2SK1764-VB - Footprint:
Package_TO_SOT_SMD:SOT-89-3 - 3D model: SOT-89 (KiCad packages3D, STEP)
- 3D model files:
2sk1764-vb-etched.step/2sk1764-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2sk1764-vb.step/2sk1764-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (8 pp, sha256
9c627b62b88180b5, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 2SK1764-VB
**VBsemi Elec** · MOSFETs · SOT-89
2SK1764-VB from VBsemi Elec, in a SOT-89. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-source voltage limit is ±20 V, and threshold voltage is 1.5 V at ID = 250 µA. |
| 2 | D | passive | Drain, connected to the exposed tab; the drain-source voltage is 60 V maximum. |
| 3 | S | passive | Source; the continuous source-drain diode current is 5.2 A at TC = 25 °C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SOT-89 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Drain-Source Voltage | VDS | | | 60 | V | | 1 |
| Maximum Power Dissipation | PD | | | 2.5 | W | TA = 25 °C, note c | 1 |
| Maximum Power Dissipation | PD | | | 1.6 | W | TA = 70 °C, note c | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Soldering Recommendations (Peak Temperature) | | | | 260 | °C | Peak temperature, notes e, f | 1 |
| Maximum Junction-to-Ambient | RthJA | | 40 | 50 | °C/W | t ≤ 5 s | 1 |
| Maximum Junction-to-Ambient | RthJA | | | 95 | °C/W | Steady State, note d | 1 |
| Maximum Junction-to-Foot (Drain) | RthJF | | 15 | 20 | °C/W | Steady State | 1 |
| Gate-Source Leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ±12 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | µA | VDS = 60 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 10 | µA | VDS = 60 V, VGS = 0 V, TJ = 55 °C | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.076 | Ω | VGS = 10 V, ID = 4.5 A | 2 |
| Total Gate Charge | Qg | | 22 | 33 | nC | VDS = 10 V, VGS = 10 V, ID = 6.3 A | 2 |
| Total Gate Charge | Qg | | 10 | 15 | nC | VDS = 10 V, VGS = 4.5 V, ID = 6.3 A | 2 |
| Turn-on Delay Time | td(on) | | 15 | 25 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Rise Time | tr | | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 35 | 55 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Fall Time | tf | | 12 | 20 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 4.5 V, Rg = 1 Ω | 2 |
| Turn-on Delay Time | td(on) | | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Rise Time | tr | | 12 | 20 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 25 | 40 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Fall Time | tf | | 10 | 15 | ns | VDD = 10 V, RL = 1.5 Ω, ID ≅ 6.7 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Body Diode Voltage | VSD | | 0.8 | 1.2 | V | IS = 6.7 A, VGS = 0 V | 2 |
| Body Diode Reverse Recovery Time | trr | | 20 | 40 | ns | IF = 6.7 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
| Body Diode Reverse Recovery Charge | Qrr | | 10 | 20 | nC | IF = 6.7 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | e. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result | 1 |
## CAD (KiCad official)
- Symbol: `2SK1764-VB`
- Footprint: `Package_TO_SOT_SMD:SOT-89-3`
- 3D model: SOT-89 (KiCad packages3D, STEP)
- 3D model files: `2sk1764-vb-etched.step` / `2sk1764-vb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `2sk1764-vb.step` / `2sk1764-vb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VBsemi Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8609092111958622208) (8 pp, sha256 `9c627b62b88180b5`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/2sk1764-vb-datasheet.pdf)