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2SJ182S-JSM

JSMSEMI · MOSFETs · TO-252

2SJ182S-JSM from JSMSEMI, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the P-channel MOSFET (Pin1); gate-source voltage rated ±25 V, with threshold VGS(th) of -1 V min to -3 V max at ID=-250 µA.
2 D passive Drain of the P-channel MOSFET (Pin2), also the tab; VDS rated -60 V and continuous drain current -15 A at TC=25°C.
3 S passive Source of the P-channel MOSFET (Pin3); RDS(ON) below 90 mΩ at VGS=-10 V, ID=-12 A.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package TO-252
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: 2SJ182S-JSM
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: 2sj182s-jsm-etched.step / 2sj182s-jsm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2sj182s-jsm.step / 2sj182s-jsm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (5 pp, sha256 338678cbbf9e7f55, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF