# 2N7002PV

**Nexperia** · MOSFETs · SOT-666

2N7002PV from Nexperia, in a SOT-666. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of transistor 1 of the dual N-channel MOSFET; the datasheet gives no pin-specific limits, and the per-transistor ratings are VDS 60 V, VGS -20 V to 20 V and ID 350 mA. |
| 2 | G1 | input | Gate terminal of transistor 1, logic-level compatible, with VGS limited to -20 V to 20 V per transistor. |
| 3 | D2 | passive | Drain terminal of transistor 2 of the dual N-channel MOSFET; the datasheet gives no pin-specific limits, and the per-transistor ratings are VDS 60 V and ID 350 mA. |
| 4 | S2 | passive | Source terminal of transistor 2 of the dual N-channel MOSFET; the datasheet gives no pin-specific limits, and the per-transistor ratings are VDS 60 V, VGS -20 V to 20 V and ID 350 mA. |
| 5 | G2 | input | Gate terminal of transistor 2, logic-level compatible, with VGS limited to -20 V to 20 V per transistor. |
| 6 | D1 | passive | Drain terminal of transistor 1 of the dual N-channel MOSFET; the datasheet gives no pin-specific limits, and the per-transistor ratings are VDS 60 V and ID 350 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-666 |
| Category | Transistors/Thyristors |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 60 | V | Per transistor | 3 |
| Gate-source voltage | VGS | -20 |  | 20 | V | Tamb = 25 °C | 3 |
| Drain current | ID |  |  | 350 | mA | VGS = 10 V; Tamb = 25 °C [1]; [1] device on FR4 PCB, mounting pad for drain 1 cm2 | 3 |
| Drain current | ID |  |  | 250 | mA | VGS = 10 V; Tamb = 100 °C [1]; [1] device on FR4 PCB, mounting pad for drain 1 cm2 | 3 |
| Peak drain current | IDM |  |  | 1.2 | A | Tamb = 25 °C; single pulse; tp ≤ 10 µs | 3 |
| Total power dissipation | Ptot |  |  | 330 | mW | Tamb = 25 °C [2]; [2] device on FR4 PCB, standard footprint | 3 |
| Total power dissipation | Ptot |  |  | 390 | mW | [1]; [1] device on FR4 PCB, mounting pad for drain 1 cm2 | 3 |
| Total power dissipation | Ptot |  |  | 1090 | mW | Tsp = 25 °C | 3 |
| Total power dissipation (per device) | Ptot |  |  | 500 | mW | Tamb = 25 °C [2]; [2] device on FR4 PCB, standard footprint | 3 |
| Junction temperature | Tj |  |  | 150 | °C |  | 3 |
| Ambient temperature | Tamb | -55 |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Source current (source-drain diode) | IS |  |  | 350 | mA | Tamb = 25 °C [1]; [1] device on FR4 PCB, mounting pad for drain 1 cm2 | 3 |
| Thermal resistance junction to ambient (per device) | Rth(j-a) |  |  | 250 | K/W | in free air [1]; [1] device on FR4 PCB, single-sided copper, tin-plated and standard footprint | 5 |
| Thermal resistance junction to ambient (per transistor) | Rth(j-a) |  | 330 | 380 | K/W | in free air [1]; [1] device on FR4 PCB, single-sided copper, tin-plated and standard footprint | 5 |
| Thermal resistance junction to ambient (per transistor) | Rth(j-a) |  | 280 | 320 | K/W | in free air [2]; [2] device on FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 1 cm2 | 5 |
| Thermal resistance junction to solder point | Rth(j-sp) |  |  | 115 | K/W |  | 5 |
| Drain-source breakdown voltage | V(BR)DSS | 60 |  |  | V | ID = 10 µA; VGS = 0 V; Tj = 25 °C | 6 |
| Gate-source threshold voltage | VGSth | 1.1 | 1.75 | 2.4 | V | ID = 250 µA; VDS=VGS; Tj = 25 °C | 6 |
| Drain leakage current | IDSS |  |  | 1 | µA | VDS = 60 V; VGS = 0 V; Tj = 25 °C | 6 |
| Drain leakage current | IDSS |  |  | 10 | µA | VDS = 60 V; VGS = 0 V; Tj = 150 °C | 6 |
| Gate leakage current | IGSS |  |  | 100 | nA | VGS = 20 V; VDS = 0 V; Tj = 25 °C | 6 |
| Gate leakage current | IGSS |  |  | -100 | nA | VGS = -20 V; VDS = 0 V; Tj = 25 °C | 6 |
| Drain-source on-state resistance | RDSon |  | 1.3 | 2 | Ω | VGS = 5 V; ID = 50 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.01; Tj = 25 °C | 6 |
| Drain-source on-state resistance | RDSon |  | 1 | 1.6 | Ω | VGS = 10 V; ID = 500 mA; pulsed; tp ≤ 300 µs; δ ≤ 0.01; Tj = 25 °C | 6 |
| Total gate charge | QG(tot) |  | 0.6 | 0.8 | nC | VDS = 30 V; ID = 300 mA; VGS = 4.5 V; Tj = 25 °C | 6 |
| Input capacitance | Ciss |  | 30 | 50 | pF | VDS = 10 V; f = 1 MHz; VGS = 0 V; Tj = 25 °C | 6 |
| Turn-on delay time | td(on) |  | 3 | 6 | ns | VDS = 50 V; RL = 250 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C | 6 |
| Turn-off delay time | td(off) |  | 10 | 20 | ns | VDS = 50 V; RL = 250 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C | 6 |
| Source-drain voltage | VSD | 0.47 | 0.75 | 1.1 | V | IS = 115 mA; VGS = 0 V; Tj = 25 °C | 6 |

## CAD (KiCad official)

- Symbol: `2N7002PV`
- Footprint: `Package_TO_SOT_SMD:SOT-666`
- 3D model: SOT-666 (KiCad packages3D, STEP)
- 3D model files: `2n7002pv-etched.step` / `2n7002pv-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `2n7002pv.step` / `2n7002pv.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/2N7002PV.pdf) (14 pp, sha256 `50e5d879eac29fb9`, retrieved 2026-10-16, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/2n7002pv-datasheet.pdf)