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2EDS8265H

Infineon Technologies · Gate Drivers · SOIC-16-300mil

2EDS8265H from Infineon Technologies, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA input Digital CMOS/TTL logic input for channel A with internal pull-down resistor to GNDI; connect to GNDI if channel is not used.
2 INB input Digital CMOS/TTL logic input for channel B with internal pull-down resistor to GNDI; connect to GNDI if channel is not used.
3 VDDI power_in Input-side supply voltage 3.3 V (internal SLDO available); a bypass capacitor to GNDI is recommended.
4 GNDI power_in Input-side ground to which all input-side signals are referenced.
5 DISABLE input Digital CMOS/TTL logic input for both channels A and B; logic high disables both output channels, with internal pull-down resistor.
6 N.C. unconnected Not connected; keep pin floating.
7 N.C. unconnected Not connected; keep pin floating.
8 SLDON input Default 3.3 V supply selected if N.C. or connected to VDDI; connected to GNDI activates SLDO allowing a supply higher than 3.5 V; internal pull-up to VDDI, hard-wired PCB connection recommended.
9 GNDB power_in Ground for output channel B.
10 OUTB output Output gate driver for channel B.
11 VDDB power_in Supply voltage for output channel B; a bypass capacitor to GNDB is recommended.
12 N.C. unconnected Not present; not connected; for channel-to-channel isolation.
13 N.C. unconnected Not connected; for channel-to-channel isolation.
14 GNDA power_in Ground for output channel A.
15 OUTA output Output gate driver for channel A.
16 VDDA power_in Supply voltage for output channel A; a bypass capacitor to GNDA is recommended.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-16-300mil
Category Motor Driver ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VDDI -0.3 4 V SLDO inactive (N.C. or connected to VDDI) 14
Output supply voltage VDDO -0.3 22 V 14
Voltage at pins PWM and DISABLE VIN -0.3 17 V 14
Voltage at pins PWM and DISABLE (transient) VIN -5 V < 50 ns for transient 14
Voltage at pins DTC and TEST/SLDO VDTC / VTEST/SLDO -0.3 V 14
Voltage at pins OUTA, OUTB VOUTA/B -0.3 V 14
Voltage at pins OUTA, OUTB (transient) VOUTA/B -2 V < 200 ns 14
Reverse current peak at pins OUTA, OUTB (source) ISRC_rev -5 Apk < 500 ns 14
Reverse current peak at pins OUTA, OUTB (sink) ISNK_rev 5 Apk 14
Non-destructive Common Mode Transient Immunity CMTI 400 V/ns input to each output channel 14
Junction temperature TJ -40 150 °C 14
Storage temperature TSTG -65 150 °C 14
Soldering temperature TSOL 260 °C reflow / wave soldering 14
ESD capability CDM VESD_CDM 0.5 kV Charged Device Model (CDM) 14
ESD capability HBM VESD_HBM 2 kV Human Body Model (HBM) 14
Input supply voltage VDDI 3 3.5 V Min. defined by UVLO 16
Output supply voltage VDDA / VDDB 4.5 20 V Min. defined by UVLO 16
Logic input voltage at pins INA, INB, DISABLE VIN 0 15 V 16
Voltage at pins DTC and SLDO VDTC / VTEST/SLDO 0 3.5 V 16
Junction temperature (operating) TJ -40 150 °C continuous operation above 125°C may reduce lifetime 16
Ambient temperature Tamb -40 125 °C 16
Undervoltage Lockout (UVLO) turn-on threshold VDDI UVLOon 2.75 2.85 2.95 V 16
UVLO threshold hysteresis VDDI UVLOhys 0.1 0.15 0.2 V 16
Undervoltage Lockout (UVLO) turn-on threshold VDDA, VDDB (8 V version) UVLO_CMon 7.6 8 8.4 V 17
UVLO threshold hysteresis VDDA, VDDB (8 V version) UVLO_CMhys 0.7 1 1.3 V 17
Input voltage threshold for transition LH VINH 1.7 2 2.3 V 17
Input voltage threshold hysteresis VIN_hys 0.4 0.8 1.2 V 17
High-level (Sourcing) Output Resistance (4 A/8 A) Ron_SRC 0.42 0.85 1.6 Ω ISNK = 50 mA 18
Peak Sourcing Output Current (4 A/8 A) ISRC_pk -4 A 18
Low-level (Sinking) Output Resistance (4 A/8 A) Ron_SNK 0.18 0.35 0.75 Ω ISRC = 50 mA 18
Peak Sinking Output Current (4 A/8 A) ISNK_pk -8 A 18
INA-/INB-to-output turn-on / turn-off propagation delay tPDon, tPDoff 31 37 44 ns 4 A/8 A version 18
DISABLE-to-output turn-on/-off propagation delay tPDDISoff 100 ns 18
Output turn-on propagation delay mismatch between channels ∆tPDon 3 ns INA, INB shorted 18
Fall time tfall 4.5 8 ns 19
Maximum transient isolation voltage VIOTM 8000 Vpk qualification for t = 60 s; production test with VIOTM > 10 kVpk for t = 1 s 23
Maximum repetitive peak isolation voltage VIORM 1420 Vpk Time Dependent Dielectric Breakdown test method 23
Maximum isolation working voltage (DC) VIOWM 1420 VDC 23
Maximum isolation working voltage (RMS) VIOWM 1000 VRMS 23
Partial discharge voltage VPD 4500 Vpk 10.2 kVpk for t = 1 s followed by partial discharge 4.5 kVpk > 1.875 x VIOWM, QPD < 5 pC; production test 23
Maximum surge isolation voltage VIOSM 6250 Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk; sample tested 23
Common Mode Transient Immunity (isolation) CMTI 150 V/ns input to each output channel; static & dynamic; sample test 23
Withstand isolation voltage VISO 5700 VRMS VISO = 5700 VRMS for t = 60 s (qualification); VISO > 1.2 x VRMS = 6840 V for t = 1 s 24
Functional isolation channel-to-channel test voltage VCh2Ch-DC-test 1500 VDC Impulse Test >10 ms; sample tested 24
Package creepage (channel-to-channel) CPG 2.4 2.5 2.7 mm Shortest distance over surface, from Output pin Ch1-GND to output pin Ch2-VDD 24
Safety supply power, input chip 20 mW RthJA = 59 K/W, Tamb = 25°C, TJ = 150°C 24
Safety supply power, Output A 1050 mW 24
Safety supply power, Output B 1050 mW 24
Safety supply power, total 2120 mW 24
Safety supply current, Output A 87.5 mA RthJA = 59 K/W, VDDA/VDDB = 12 V, Tamb = 25°C, TJ = 150°C 24
Safety supply current, Output B 87.5 mA RthJA = 59 K/W, VDDA/VDDB = 12 V, Tamb = 25°C, TJ = 150°C 24
Safety supply current, Output A 53.5 mA RthJA = 59 K/W, VDDA/VDDB = 20 V, Tamb = 25°C, TJ = 150°C 24
Safety supply current, Output B 53.5 mA RthJA = 59 K/W, VDDA/VDDB = 20 V, Tamb = 25°C, TJ = 150°C 24
Safety temperature Ts 150 °C Ts = TJ,max 24
Thermal resistance junction-ambient (PG-DSO-16-30, WB) RthJA 59 K/W 15
Thermal resistance junction-case (top) (PG-DSO-16-30, WB) RthJC 32 K/W 15
Thermal resistance junction-board (PG-DSO-16-30, WB) RthJB 33 K/W 15
Characterization parameter junction-top (PG-DSO-16-30, WB) ΨthJT 8.9 K/W 15
Characterization parameter junction-board (PG-DSO-16-30, WB) ΨthJB 7.7 K/W 15

CAD (KiCad official)

  • Symbol: 2EDS8265H
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: 2eds8265h-etched.step / 2eds8265h-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2eds8265h.step / 2eds8265h.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (38 pp, sha256 6da31bc3361e73a6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF