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2EDS7165HXUMA1

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Infineon Technologies Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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2EDS7165HXUMA1

Infineon Technologies · Gate Drivers · SOIC-16-300mil

2EDS7165HXUMA1 from Infineon Technologies, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA input Digital CMOS/TTL logic input for channel A with internal pull-down resistor to GNDI; connect to GNDI if channel is unused.
2 INB input Digital CMOS/TTL logic input for channel B with internal pull-down resistor to GNDI; connect to GNDI if channel is unused.
3 VDDI power_in Input-side supply voltage 3.3 V (internal SLDO available); a bypass capacitor from VDDI to GNDI is recommended.
4 GNDI power_in Input-side ground to which all input-side signals are referenced.
5 DISABLE input Digital CMOS/TTL logic input for both channels A and B; logic high disables both output channels, with internal pull-down resistor.
6 N.C. unconnected Not connected; keep pin floating.
7 N.C. unconnected Not connected; keep pin floating.
8 SLDON input Default 3.3 V supply selected if N.C. or connected to VDDI; connecting to GNDI activates the SLDO so a VDDI higher than 3.5 V can be used, with internal pull-up to VDDI and hard-wired PCB connection recommended.
9 GNDB power_in Ground for output channel B.
10 OUTB output Gate driver output for channel B.
11 VDDB power_in Supply voltage for output channel B; a bypass capacitor from VDDB to GNDB is recommended.
12 N.C. unconnected Not connected, for channel-to-channel isolation.
13 N.C. unconnected Not connected, for channel-to-channel isolation.
14 GNDA power_in Ground for output channel A.
15 OUTA output Gate driver output for channel A.
16 VDDA power_in Supply voltage for output channel A; a bypass capacitor from VDDA to GNDA is recommended.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-16-300mil
Category Motor Driver ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage at pin VDDI VDDI -0.3 4 V if SLDO activated, input-side supply can be higher 12
Output supply voltage VDDO -0.3 22 V 12
Voltage at pins PWM and DISABLE VIN -0.3 17 V 12
Voltage at pins PWM and DISABLE transient VIN -5 V < 50 ns for transient 12
Reverse current peak source ISRC_rev -5 Apk < 500 ns 12
Reverse current peak sink ISNK_rev 5 Apk < 500 ns 12
Non-destructive Common Mode Transient Immunity CMTI 400 V/ns input to each output channel 12
Junction temperature TJ -40 150 °C 12
Storage temperature TSTG -65 150 °C 12
Soldering temperature TSOL 260 °C reflow 12
ESD capability CDM VESD_CDM 0.5 kV Charged Device Model 12
ESD capability HBM VESD_HBM 2 kV Human Body Model 12
Voltage at pin VDDI (operating) VDDI 3 3.5 V Min. defined by UVLO 14
Logic input voltage at pins INA, INB, DISABLE VIN 0 15 V 14
Voltage at pin SLDO (operating) VSLDO 0 3.5 V 14
Junction temperature (operating) TJ -40 150 °C continuous operation above 125°C may reduce lifetime 14
Ambient temperature Tamb -40 125 °C 14
Thermal resistance junction-ambient RthJA25 59 K/W PG-DSO-16-30, Tamb=25°C 13
Thermal resistance junction-case (top) RthJC25 32 K/W PG-DSO-16-30, Tamb=25°C 13
Thermal resistance junction-board RthJB25 33 K/W PG-DSO-16-30, Tamb=25°C 13
Characterization parameter junction-top ΨthJT25 8.9 K/W PG-DSO-16-30, Tamb=25°C 13
Characterization parameter junction-board ΨthJB25 7.7 K/W PG-DSO-16-30, Tamb=25°C 13
UVLO turn-on threshold VDDI UVLOon 2.75 2.85 2.95 V 14
UVLO turn-off threshold VDDI UVLOoff 2.7 V 14
UVLO threshold hysteresis VDDI UVLOhys 0.1 0.15 0.2 V 14
UVLO turn-on threshold VDDA, VDDB (4 V version) UVLO_CMon 4 4.2 4.4 V 15
UVLO turn-off threshold VDDA, VDDB (4 V version) UVLO_CMoff 3.9 V 15
UVLO threshold hysteresis VDDA, VDDB (4 V version) UVLO_CMhys 0.2 0.3 0.4 V 15
Input voltage threshold for transition LH VINH 1.65 2 2.35 V 15
Input voltage threshold for transition HL VINL 1.2 V 15
Input voltage threshold hysteresis VIN_hys 0.4 0.8 1.2 V 15
Input pull-down resistor RIN 150 kΩ 15
High-level (Sourcing) Output Resistance Ron_SRC 1.4 3.1 5.8 Ω ISNK = 50 mA 16
Peak Sourcing Output Current ISRC_pk 1 A 16
Low-level (Sinking) Output Resistance Ron_SNK 0.6 1.2 2.5 Ω ISRC = 50 mA 16
Peak Sinking Output Current ISNK_pk -2 A 16
INA-/INB-to-output turn-on propagation delay tPDon 31 37 44 ns 1 A/2 A version 16
INA-/INB-to-output turn-off propagation delay tPDoff 29 35 44 ns 1 A/2 A version 16
DISABLE-to-output turn-on/-off propagation delay tPDDISoff 100 ns 16
Output turn-on propagation delay mismatch between channels ΔtPDon 3 ns INA, INB shorted 16
Fall time tfall 4.5 8 ns 17
Minimum input pulse width that changes output state tPW 18 ns 17
IVDDI quiescent current IVDDIqu1 1.4 mA no switching 14
IVDDA, IVDDB quiescent current IVDDAqu2 / IVDDBqu2 0.6 mA Outx = low, no switching (4 V, 8 V UVLO options) 14
Input-side start-up time tSTART,VDDI 7 µs see Figure 5 17
Input-side deactivation time tSTOP,VDDI 255 ns see Figure 5 17
Output-side start-up time tSTART,VDDA/B 5 µs see Figure 5 17
Output-side deactivation time tSTOP,VDDA/B 110 ns see Figure 5 17
Maximum transient isolation voltage VIOTM 8000 Vpk qualification for t = 60 s 21
Maximum repetitive peak isolation voltage VIORM 1420 Vpk Time Dependent Dielectric Breakdown test method 21
Maximum surge isolation voltage VIOSM 6250 Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk; sample tested 21
Withstand isolation voltage VISO 5700 VRMS t = 60 s (qualification) 22
Common Mode Transient Immunity CMTI 150 V/ns according to DIN V VDE V0884-11, static and dynamic test 21
Package clearance CLR 8 mm from any input pin to any output pin 21
Package creepage CPG 8 mm from any input pin to any output pin 21
Capacitance input-to-output CIO 2 pF 21
Safety temperature Ts 150 °C Ts = TJ,max 22

CAD (KiCad official)

  • Symbol: 2EDS7165HXUMA1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: 2eds7165hxuma1-etched.step / 2eds7165hxuma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2eds7165hxuma1.step / 2eds7165hxuma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (38 pp, sha256 0faf89a1f22388e0, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF