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2EDR8259HXUMA1

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Infineon Technologies Gate Drive ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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2EDR8259HXUMA1

Infineon Technologies · Gate Drive ICs · SOIC-16

2EDR8259HXUMA1 from Infineon Technologies, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INA input Input signal for channel A, a logic input with TTL compatible thresholds and an internal pull-down resistor.
2 INB input Input signal for channel B, a logic input with TTL compatible thresholds and an internal pull-down resistor.
3 VDDI power_in Input-side supply voltage with an operating range of 3 V to 17 V, shorted externally with pin 8.
4 GNDI power_in Primary-side ground.
5 DIS input Active-high disable input for channels A and B; low or open lets INA/INB control OUTA/OUTB, high forces OUTA/OUTB low.
6 STP/DTC input Shoot-through protection and dead-time control; high or open disables STP/DTC, a resistor RDTC to GNDI sets dead-time tdt [ns] = 10 x RDTC [kΩ], and a direct connection to GNDI enables STP only (avoid capacitors on this pin).
7 N.C. unconnected No internal connection.
8 VDDI power_in Input-side supply voltage with an operating range of 3 V to 17 V, shorted externally with pin 3.
9 GNDB power_in Secondary-side ground for channel B.
10 OUTB output Secondary-side channel B output, low-impedance with source and sink capability.
11 VDDB power_in Secondary-side channel B supply with an operating range of UVLO to 20 V.
12 N.C. unconnected No internal connection.
13 N.C. unconnected No internal connection.
14 GNDA power_in Secondary-side ground for channel A.
15 OUTA output Secondary-side channel A output, low-impedance with source and sink capability.
16 VDDA power_in Secondary-side channel A supply with an operating range of UVLO to 20 V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-16
Category Power Management
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VDDI -0.3 18 V 10
Output supply voltage VDDA, VDDB -0.3 22 V 10
Voltage at INA, INB, DIS/EN (DC) VIN -0.3 18 V 10
Voltage at INA, INB, DIS/EN (transient) VIN -5 V transient for 50 ns 10
Reverse current peak at OUTA, OUTB ISRC_rev -5 Apk transient for 500 ns 10
Reverse current peak at OUTA, OUTB ISNK_rev 5 Apk transient for 500 ns 10
Junction temperature TJ -40 150 °C 10
Storage temperature TSTG -65 150 °C 10
Soldering temperature TSOL 260 °C reflow 10
ESD capability CDM VESD_CDM 0.5 kV Charged Device Model 10
ESD capability HBM VESD_HBM 2 kV Human Body Model 10
Input supply voltage at VDDI VDDI 3 17 V Min. defined by UVLOVDDI 12
Output supply voltage at VDDA and VDDB VDDA, VDDB 8.5 20 V 8 V UVLO option 12
Input voltage at INA, INB, DIS/EN VIN 0 17 V 12
Junction temperature TJ -40 150 °C 12
Ambient temperature TA -40 125 °C 12
Thermal resistance junction-case (top) RthJC 46 K/W 1s0p and 2s2p, TA = 25°C 11
Thermal resistance junction-ambient RthJA25 107 K/W 1s0p, TA = 25°C 11
Thermal resistance junction-ambient RthJA25 69 K/W 2s2p, TA = 25°C 11
Thermal resistance junction-ambient RthJA85 95 K/W 1s0p 11
Thermal resistance junction-ambient RthJA85 65 K/W 2s2p 11
Thermal resistance junction-board RthJB 27 K/W 2s2p 11
IVDDI quiescent current IVDDIq 1.67 2.12 mA no switching 12
IVDDA/B quiescent current IVDDA/Bq 0.62 0.86 mA OUT = low, VDDA/B = 12 V 12
IVDDA/B quiescent current IVDDA/Bq 0.66 0.89 mA OUT = low, VDDA/B = 18 V 12
IVDDA/B quiescent current IVDDA/Bq 0.76 1 mA OUT = high, VDDA/B = 12 V 12
IVDDA/B quiescent current IVDDA/Bq 0.9 1.14 mA OUT = high, VDDA/B = 18 V 12
UVLO turn-on threshold VDDI UVLOVDDI,on 2.85 2.95 V 13
UVLO turn-off threshold VDDI UVLOVDDI,off 2.55 2.7 V 13
UVLO threshold hysteresis VDDI UVLOVDDI,hys 0.1 0.15 0.2 V 13
UVLO turn-on threshold VDDA, VDDB (8 V option) UVLOVDDA,on / UVLOVDDB,on 8 8.5 V 13
UVLO turn-off threshold VDDA, VDDB (8 V option) UVLOVDDA,off / UVLOVDDB,off 6.6 7 V 13
UVLO threshold hysteresis VDDA, VDDB (8 V option) UVLOVDDA,hys / UVLOVDDB,hys 0.7 1 1.3 V 13
Input voltage threshold for transition LH VINH 2 2.36 V 14
Input voltage threshold for transition HL VINL 0.9 1.2 V 14
Input voltage threshold hysteresis VIN_hys 0.38 0.8 1.2 V 14
High-level input leakage current IIN 22 27 µA INA/INB pin tied to VDDI 14
Input pull-down resistor RIN,PD 150 kΩ 14
Dead-time tdt 85 100 115 ns RDTC = 10 kΩ 15
Dead-time tdt 255 300 345 ns RDTC = 30 kΩ 15
Dead-time tdt 800 950 1100 ns RDTC = 100 kΩ 15
Channel-to-channel dead-time mismatch ∆tdt,Ch-Ch 0 10 ns RDTC = 10 kΩ 15
Part-to-part dead-time mismatch ∆tdt,p-p 0 20 ns RDTC = 10 kΩ 15
High-level (sourcing) output resistance Ron_SRC 0.6 0.95 1.5 Ω ISRC = 50 mA 15
Low-level (sinking) output resistance Ron_SNK 0.24 0.39 0.62 Ω ISNK = 50 mA 15
INx to OUTx turn-on propagation delay tPDon,INx 33 38 47 ns See Figure 5, Figure 6 15
INx to OUTx turn-off propagation delay tPDoff,INx 30 36 46 ns See Figure 5, Figure 6 16
Part-to-part turn-on propagation delay mismatch ∆tPDon,p-p 0 6 ns 16
Part-to-part turn-off propagation delay mismatch ∆tPDoff,p-p 0 8 ns 16
Channel-to-channel turn-on propagation delay mismatch tPDon,ChA-ChB -4 4 ns See Figure 7 16
Channel-to-channel turn-off propagation delay mismatch ∆tPDoff,ChA-ChB -5.5 3 ns See Figure 7 16
Pulse width distortion tPWD -5 2 5.5 ns See Figure 8 16
Rise time trise 7.5 14 ns CLOAD = 1.8 nF, see Figure 10 16
Fall time tfall 6 11 ns CLOAD = 1.8 nF, see Figure 10 16
Minimum input pulse width that changes output state tPW 10 17 25 ns See Figure 11 16
Input-side start-up time tSTART,VDDI 3.5 5 µs see Figure 12 16
Input-side deactivation time tSTOP,VDDI 600 750 ns see Figure 12 16
Output-side start-up time tSTART,VDDA/B 2.5 5 µs see Figure 13 16
Output-side deactivation time tSTOP,VDDA/B 500 800 ns see Figure 13 16
Static Common-Mode Transient Immunity (high) /CMStatic,H/ 150 V/ns VCM = 1500 V; INA, INB tied to VDDI (logic high inputs) 17

CAD (KiCad official)

  • Symbol: 2EDR8259HXUMA1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 2edr8259hxuma1-etched.step / 2edr8259hxuma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2edr8259hxuma1.step / 2edr8259hxuma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (34 pp, sha256 b16f076b61f2415f, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF