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2EDN8534FXTMA1
Public Made by Adomby adom
Infineon Technologies Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown2EDN8534FXTMA1
Infineon Technologies · Gate Drivers · SOIC-8
2EDN8534FXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Enable input for channel A: if ENA is high or left open, OUTA is controlled by INA, and if ENA is low, OUTA is forced low. |
| 2 | INA | input | Logic input signal for channel A that controls OUTA. |
| 3 | GND | power_in | Gate driver reference ground. |
| 4 | INB | input | Logic input signal for channel B that controls OUTB. |
| 5 | OUTB | output | Low-impedance driver output for channel B with source and sink capability. |
| 6 | VDD | power_in | Positive supply voltage with an operating range of 4.5 V/8.6 V to 20 V. |
| 7 | OUTA | output | Low-impedance driver output for channel A with source and sink capability. |
| 8 | ENB | input | Enable input for channel B: if ENB is high or left open, OUTB is controlled by INB, and if ENB is low, OUTB is forced low. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VDD | -0.3 | 22 | V | 13 | ||
| Voltage at pins INA, INB, ENA, ENB | VIN | -12 | 22 | V | 13 | ||
| Voltage at pins OUTA, OUTB | VOUT | -0.3 | V | Printed max VDD+ 0.3 V; voltage spikes from reverse current peaks allowed (note 1) | 13 | ||
| Voltage at pins OUTA, OUTB (repetitive pulse) | VOUT | -2 | V | Repetitive pulse < 200 ns; printed max VDD+2 V (note 2) | 13 | ||
| Reverse current peak at pins OUTA, OUTB | ISNKREV, ISRCREV | -5 | 5 | A | Apk < 500 ns | 13 | |
| Junction temperature | TJ | -40 | 150 | °C | 13 | ||
| Storage temperature | TS | -55 | 150 | °C | 13 | ||
| ESD capability | VESD | 0.5 | kV | Charged Device Model (CDM), JESD22-002 | 13 | ||
| ESD capability | VESD | 2 | kV | Human Body Model (HBM), JESD22-A114-B | 13 | ||
| Supply voltage | VDD | 4.5 | 20 | V | Min. defined by UVLO | 15 | |
| Logic input voltage | VIN | -10 | 20 | V | 15 | ||
| Junction temperature (operating) | TJ | -40 | 150 | °C | Continuous operation above 125°C may reduce life time (note 1) | 15 | |
| VDD quiescent current, OUT = high | IVDDQU1 | 0.5 | 0.9 | 1.2 | mA | OUT = high, VDD = 12 V | 15 |
| VDD quiescent current, OUT = low | IVDDQU2 | 0.3 | 0.5 | 0.7 | mA | OUT = low, VDD = 12 V | 15 |
| Undervoltage lockout turn on threshold (8 V version) | UVLOON | 8 | 8.6 | V | 15 | ||
| Undervoltage lockout turn off threshold (8 V version) | UVLOOFF | 6.5 | 7 | V | 15 | ||
| UVLO threshold hysteresis (8 V version) | UVLOHYS | 0.8 | 1 | 1.2 | V | 15 | |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | 16 | |
| Input voltage threshold for transition HL | VINL | 1 | 1.2 | 1.4 | V | 16 | |
| High level (sourcing) output resistance (2EDN853x) | RONSRC | 0.4 | 0.8 | 1.4 | Ω | ISRC = 50 mA | 16 |
| Low level (sinking) output resistance (2EDN853x) | RONSNK | 0.35 | 0.6 | 1.2 | Ω | ISNK = 50 mA | 16 |
| Input/Enable to output propagation delay, low to high | tPDlh | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable | 17 |
| Input/Enable to output propagation delay, high to low | tPDhl | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; high to low transition at Input/Enable | 17 |
| Input/Enable to output propagation delay mismatch between the two channels on the same IC | ΔtPD | 2 | ns | 17 | |||
| Rise time | tRISE | 8.6 | 15 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 | |
| Fall time | tFALL | 6 | 13 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 | |
| Minimum input pulse width that changes output state | tPW | 6 | 10 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 | |
| Thermal resistance junction-ambient (PG-DSO-8) | RthJA25 | 111 | K/W | PG-DSO-8, Tamb = 25°C | 13 | ||
| Thermal resistance junction-case (top) (PG-DSO-8) | RthJC25 | 66 | K/W | PG-DSO-8, Tamb = 25°C | 13 | ||
| Thermal resistance junction-board (PG-DSO-8) | RthJB25 | 59 | K/W | PG-DSO-8, Tamb = 25°C | 13 | ||
| Characterization parameter junction-top (PG-DSO-8) | ΨthJC25 | 12 | K/W | PG-DSO-8, Tamb = 25°C | 13 | ||
| Characterization parameter junction-board (PG-DSO-8) | ΨthJB25 | 57 | K/W | PG-DSO-8, Tamb = 25°C | 13 |
CAD (KiCad official)
- Symbol:
2EDN8534FXTMA1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
2edn8534fxtma1-etched.step/2edn8534fxtma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2edn8534fxtma1.step/2edn8534fxtma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (36 pp, sha256
5adb1dc38d25805d, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).