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2EDN8533FXTMA1

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Infineon Technologies Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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2EDN8533FXTMA1

Infineon Technologies · Gate Drive ICs · SOIC-8

2EDN8533FXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENA input Enable input for channel A: if ENA is high or left open OUTA is controlled by INA, and ENA low causes OUTA low.
2 INA input Logic input signal for channel A, controlling OUTA (inverting for this 2EDN8533F version).
3 GND power_in Gate driver reference ground.
4 INB input Logic input signal for channel B, controlling OUTB (inverting for this 2EDN8533F version).
5 OUTB output Channel B driver output, low-impedance with source and sink capability.
6 VDD power_in Positive supply voltage with an operating range of 4.5 V/8.6 V to 20 V (8.6 V to 20 V applies to the 8 V UVLO 2EDN8533F).
7 OUTA output Channel A driver output, low-impedance with source and sink capability.
8 ENB input Enable input for channel B: if ENB is high or left open OUTB is controlled by INB, and ENB low causes OUTB low.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Power Supply Chip
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive supply voltage VDD -0.3 22 V 13
Voltage at pins INA, INB, ENA, ENB VIN -12 22 V 13
Reverse current peak at pins OUTA, OUTB ISNKREV, ISRCREV -5 5 Apk < 500 ns 13
Junction temperature TJ -40 150 °C 13
Storage temperature TS -55 150 °C 13
ESD capability CDM VESD 0.5 kV Charged Device Model (CDM) 13
ESD capability HBM VESD 2 kV Human Body Model (HBM) 13
Supply voltage VDD 4.5 20 V Min. defined by UVLO 15
Logic input voltage VIN -10 20 V 15
Junction temperature TJ -40 150 °C Continuous operation above 125°C may reduce life time 15
VDD quiescent current, output high IVDDQU1 0.5 0.9 1.2 mA OUT = high, VDD = 12 V 15
VDD quiescent current, output low IVDDQU2 0.3 0.5 0.7 mA OUT = low, VDD = 12 V 15
UVLO turn on threshold UVLOON 8 8.6 V 15
UVLO turn off threshold UVLOOFF 6.5 7 V 15
UVLO threshold hysteresis UVLOHYS 0.8 1 1.2 V 15
Input voltage threshold for transition LH VINH 1.9 2.1 2.3 V 16
Input voltage threshold for transition HL VINL 1 1.2 1.4 V 16
High level (sourcing) output resistance RONSRC 0.4 0.8 1.4 Ω ISRC = 50 mA 16
Low level (sinking) output resistance RONSNK 0.35 0.6 1.2 Ω ISNK = 50 mA 16
Input/Enable to output propagation delay, low to high tPDlh 15 19 25 ns CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable 17
Input/Enable to output propagation delay, high to low tPDhl 15 19 25 ns CLOAD= 1.8 nF, VDD= 12 V; high to low transition at Input/Enable 17
Propagation delay mismatch between the two channels ∆tPD 2 ns 17
Rise time tRISE 8.6 15 ns CLOAD = 1.8 nF, VDD = 12 V 17
Fall time tFAll 6 13 ns CLOAD = 1.8 nF, VDD = 12 V 17
Minimum input pulse width that changes output state tPW 6 10 ns CLOAD = 1.8 nF, VDD = 12 V 17
Input pull up resistor RINH 400 kΩ Inputs with initial high logic level 16
Input pull down resistor RINL 100 kΩ Inputs with initial low logic level 16
High level (sourcing) output current ISRCPEAK 5 A 16
Low level (sinking) output current ISNKPEAK -5 A 16
VDD start-up time from UVLOON to OUTx tSTART 1.8 µs VDD rising to 12 V; see Figure 11 17
VDD deactivation time from UVLOOFF to OUTx tSTOP 500 ns VDD falling from 12 V; see Figure 11 17
Activation time of output clamping in UVLO condition tCLAMP,OUT 20 ns see Figure 13 17
Thermal resistance junction-ambient, PG-DSO-8 RthJA25 111 K/W PG-DSO-8, Tamb = 25°C 13
Thermal resistance junction-case (top), PG-DSO-8 RthJC25 66 K/W PG-DSO-8, Tamb = 25°C 13
Thermal resistance junction-board, PG-DSO-8 RthJB25 59 K/W PG-DSO-8, Tamb = 25°C 13
Characterization parameter junction-top, PG-DSO-8 ΨthJC25 12 K/W PG-DSO-8, Tamb = 25°C 13
Characterization parameter junction-board, PG-DSO-8 ΨthJB25 57 K/W PG-DSO-8, Tamb = 25°C 13

CAD (KiCad official)

  • Symbol: 2EDN8533FXTMA1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 2edn8533fxtma1-etched.step / 2edn8533fxtma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2edn8533fxtma1.step / 2edn8533fxtma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (36 pp, sha256 1d800411d8bcdaff, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF