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2EDN7534FXTMA1
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Infineon Technologies Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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2EDN7534FXTMA1
Infineon Technologies · Gate Drive ICs · SOIC-8
2EDN7534FXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Enable input for channel A: if ENA is high or left open, OUTA is controlled by INA, and a low level on ENA forces OUTA low. |
| 2 | INA | input | Logic input controlling OUTA, configured as inverting or non-inverting depending on the product version (this 2EDN7534F variant is non-inverting/direct). |
| 3 | GND | power_in | Gate driver reference ground. |
| 4 | INB | input | Logic input controlling OUTB, configured as inverting or non-inverting depending on the product version (this 2EDN7534F variant is non-inverting/direct). |
| 5 | OUTB | output | Low-impedance driver output for channel B with source and sink capability. |
| 6 | VDD | power_in | Positive supply voltage with an operating range printed as 4.5 V/8.6 V to 20 V. |
| 7 | OUTA | output | Low-impedance driver output for channel A with source and sink capability. |
| 8 | ENB | input | Enable input for channel B: if ENB is high or left open, OUTB is controlled by INB, and a low level on ENB forces OUTB low. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VDD | -0.3 | 22 | V | 13 | ||
| Voltage at pins INA, INB, ENA, ENB | VIN | -12 | 22 | V | 13 | ||
| Voltage at pins OUTA, OUTB | VOUT | -0.3 | V | max = VDD+0.3 V (note 1: voltage spikes from reverse current peaks allowed) | 13 | ||
| Voltage at pins OUTA, OUTB (repetitive pulse) | VOUT | -2 | V | max = VDD+2 V; repetitive pulse < 200 ns (note 2: values verified by characterization) | 13 | ||
| Reverse current peak at pins OUTA, OUTB | ISNKREV / ISRCREV | -5 | 5 | A | Apk < 500 ns | 13 | |
| Junction temperature | TJ | -40 | 150 | °C | 13 | ||
| Storage temperature | TS | -55 | 150 | °C | 13 | ||
| ESD capability (CDM) | VESD | 0.5 | kV | Charged Device Model (CDM), per JESD22-002 | 13 | ||
| ESD capability (HBM) | VESD | 2 | kV | Human Body Model (HBM), per JESD22-A114-B | 13 | ||
| Supply voltage | VDD | 4.5 | 20 | V | Min. defined by UVLO | 15 | |
| Logic input voltage | VIN | -10 | 20 | V | 15 | ||
| Junction temperature (operating) | TJ | -40 | 150 | °C | Continuous operation above 125°C may reduce life time | 15 | |
| VDD quiescent current, OUT high | IVDDQU1 | 0.5 | 0.9 | 1.2 | mA | OUT = high, VDD = 12 V | 15 |
| VDD quiescent current, OUT low | IVDDQU2 | 0.3 | 0.5 | 0.7 | mA | OUT = low, VDD = 12 V | 15 |
| Undervoltage lockout (UVLO) turn on threshold | UVLOON | 4.2 | 4.5 | V | 15 | ||
| Undervoltage lockout (UVLO) turn off threshold | UVLOOFF | 3.6 | 3.9 | V | 15 | ||
| UVLO threshold hysteresis | UVLOHYS | 0.25 | 0.3 | 0.35 | V | 15 | |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | 16 | |
| Input voltage threshold for transition HL | VINL | 1 | 1.2 | 1.4 | V | 16 | |
| High level (sourcing) output resistance | RONSRC | 0.4 | 0.8 | 1.4 | Ω | ISRC = 50 mA | 16 |
| Low level (sinking) output resistance | RONSNK | 0.35 | 0.6 | 1.2 | Ω | ISNK = 50 mA | 16 |
| Input/Enable to output propagation delay, low to high | tPDlh | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable | 17 |
| Input/Enable to output propagation delay, high to low | tPDhl | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; high to low transition at Input/Enable | 17 |
| Input/Enable to output propagation delay mismatch between the two channels on the same IC | ∆tPD | 2 | ns | 17 | |||
| Rise time | tRISE | 8.6 | 15 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 | |
| Fall time | tFALL | 6 | 13 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 | |
| Minimum input pulse width that changes output state | tPW | 6 | 10 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 | |
| High level (sourcing) output current | ISRCPEAK | 5 | A | Not subject to production test | 16 | ||
| Low level (sinking) output current | ISNKPEAK | -5 | A | Not subject to production test | 16 | ||
| Input pull up resistor | RINH | 400 | kΩ | Inputs with initial high logic level | 16 | ||
| Input pull down resistor | RINL | 100 | kΩ | Inputs with initial low logic level | 16 | ||
| VDD start-up time from UVLOON to OUTx | tSTART | 1.8 | µs | VDD rising to 12 V; see Figure 11 (not subject to production test) | 17 | ||
| VDD deactivation time from UVLOOFF to OUTx | tSTOP | 500 | ns | VDD falling from 12 V; see Figure 11 (not subject to production test) | 17 | ||
| Activation time of output clamping in UVLO condition | tCLAMP,OUT | 20 | ns | see Figure 13 (not subject to production test) | 17 | ||
| Thermal resistance junction-ambient, PG-DSO-8 | RthJA | 111 | K/W | PG-DSO-8, Tamb = 25°C (note 1: natural convection, JEDEC high-K board) | 13 | ||
| Thermal resistance junction-case (top), PG-DSO-8 | RthJC | 66 | K/W | PG-DSO-8, Tamb = 25°C (note 2: cold plate on package top) | 13 | ||
| Thermal resistance junction-board, PG-DSO-8 | RthJB | 59 | K/W | PG-DSO-8, Tamb = 25°C (note 3: ring cold plate, JESD51-8) | 13 | ||
| Characterization parameter junction-top, PG-DSO-8 | ΨthJC | 12 | K/W | PG-DSO-8, Tamb = 25°C (note 4) | 13 | ||
| Characterization parameter junction-board, PG-DSO-8 | ΨthJB | 57 | K/W | PG-DSO-8, Tamb = 25°C (note 5) | 13 |
CAD (KiCad official)
- Symbol:
2EDN7534FXTMA1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
2edn7534fxtma1-etched.step/2edn7534fxtma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2edn7534fxtma1.step/2edn7534fxtma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (36 pp, sha256
e08bf597f6c026a0, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 2EDN7534FXTMA1
**Infineon Technologies** · Gate Drive ICs · SOIC-8
2EDN7534FXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENA | input | Enable input for channel A: if ENA is high or left open, OUTA is controlled by INA, and a low level on ENA forces OUTA low. |
| 2 | INA | input | Logic input controlling OUTA, configured as inverting or non-inverting depending on the product version (this 2EDN7534F variant is non-inverting/direct). |
| 3 | GND | power_in | Gate driver reference ground. |
| 4 | INB | input | Logic input controlling OUTB, configured as inverting or non-inverting depending on the product version (this 2EDN7534F variant is non-inverting/direct). |
| 5 | OUTB | output | Low-impedance driver output for channel B with source and sink capability. |
| 6 | VDD | power_in | Positive supply voltage with an operating range printed as 4.5 V/8.6 V to 20 V. |
| 7 | OUTA | output | Low-impedance driver output for channel A with source and sink capability. |
| 8 | ENB | input | Enable input for channel B: if ENB is high or left open, OUTB is controlled by INB, and a low level on ENB forces OUTB low. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VDD | -0.3 | | 22 | V | | 13 |
| Voltage at pins INA, INB, ENA, ENB | VIN | -12 | | 22 | V | | 13 |
| Voltage at pins OUTA, OUTB | VOUT | -0.3 | | | V | max = VDD+0.3 V (note 1: voltage spikes from reverse current peaks allowed) | 13 |
| Voltage at pins OUTA, OUTB (repetitive pulse) | VOUT | -2 | | | V | max = VDD+2 V; repetitive pulse < 200 ns (note 2: values verified by characterization) | 13 |
| Reverse current peak at pins OUTA, OUTB | ISNKREV / ISRCREV | -5 | | 5 | A | Apk < 500 ns | 13 |
| Junction temperature | TJ | -40 | | 150 | °C | | 13 |
| Storage temperature | TS | -55 | | 150 | °C | | 13 |
| ESD capability (CDM) | VESD | | | 0.5 | kV | Charged Device Model (CDM), per JESD22-002 | 13 |
| ESD capability (HBM) | VESD | | | 2 | kV | Human Body Model (HBM), per JESD22-A114-B | 13 |
| Supply voltage | VDD | 4.5 | | 20 | V | Min. defined by UVLO | 15 |
| Logic input voltage | VIN | -10 | | 20 | V | | 15 |
| Junction temperature (operating) | TJ | -40 | | 150 | °C | Continuous operation above 125°C may reduce life time | 15 |
| VDD quiescent current, OUT high | IVDDQU1 | 0.5 | 0.9 | 1.2 | mA | OUT = high, VDD = 12 V | 15 |
| VDD quiescent current, OUT low | IVDDQU2 | 0.3 | 0.5 | 0.7 | mA | OUT = low, VDD = 12 V | 15 |
| Undervoltage lockout (UVLO) turn on threshold | UVLOON | | 4.2 | 4.5 | V | | 15 |
| Undervoltage lockout (UVLO) turn off threshold | UVLOOFF | 3.6 | 3.9 | | V | | 15 |
| UVLO threshold hysteresis | UVLOHYS | 0.25 | 0.3 | 0.35 | V | | 15 |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | | 16 |
| Input voltage threshold for transition HL | VINL | 1 | 1.2 | 1.4 | V | | 16 |
| High level (sourcing) output resistance | RONSRC | 0.4 | 0.8 | 1.4 | Ω | ISRC = 50 mA | 16 |
| Low level (sinking) output resistance | RONSNK | 0.35 | 0.6 | 1.2 | Ω | ISNK = 50 mA | 16 |
| Input/Enable to output propagation delay, low to high | tPDlh | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable | 17 |
| Input/Enable to output propagation delay, high to low | tPDhl | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; high to low transition at Input/Enable | 17 |
| Input/Enable to output propagation delay mismatch between the two channels on the same IC | ∆tPD | | | 2 | ns | | 17 |
| Rise time | tRISE | | 8.6 | 15 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 |
| Fall time | tFALL | | 6 | 13 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 |
| Minimum input pulse width that changes output state | tPW | | 6 | 10 | ns | CLOAD = 1.8 nF, VDD = 12 V (not subject to production test) | 17 |
| High level (sourcing) output current | ISRCPEAK | | 5 | | A | Not subject to production test | 16 |
| Low level (sinking) output current | ISNKPEAK | | -5 | | A | Not subject to production test | 16 |
| Input pull up resistor | RINH | | 400 | | kΩ | Inputs with initial high logic level | 16 |
| Input pull down resistor | RINL | | 100 | | kΩ | Inputs with initial low logic level | 16 |
| VDD start-up time from UVLOON to OUTx | tSTART | | 1.8 | | µs | VDD rising to 12 V; see Figure 11 (not subject to production test) | 17 |
| VDD deactivation time from UVLOOFF to OUTx | tSTOP | | 500 | | ns | VDD falling from 12 V; see Figure 11 (not subject to production test) | 17 |
| Activation time of output clamping in UVLO condition | tCLAMP,OUT | | 20 | | ns | see Figure 13 (not subject to production test) | 17 |
| Thermal resistance junction-ambient, PG-DSO-8 | RthJA | | 111 | | K/W | PG-DSO-8, Tamb = 25°C (note 1: natural convection, JEDEC high-K board) | 13 |
| Thermal resistance junction-case (top), PG-DSO-8 | RthJC | | 66 | | K/W | PG-DSO-8, Tamb = 25°C (note 2: cold plate on package top) | 13 |
| Thermal resistance junction-board, PG-DSO-8 | RthJB | | 59 | | K/W | PG-DSO-8, Tamb = 25°C (note 3: ring cold plate, JESD51-8) | 13 |
| Characterization parameter junction-top, PG-DSO-8 | ΨthJC | | 12 | | K/W | PG-DSO-8, Tamb = 25°C (note 4) | 13 |
| Characterization parameter junction-board, PG-DSO-8 | ΨthJB | | 57 | | K/W | PG-DSO-8, Tamb = 25°C (note 5) | 13 |
## CAD (KiCad official)
- Symbol: `2EDN7534FXTMA1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `2edn7534fxtma1-etched.step` / `2edn7534fxtma1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `2edn7534fxtma1.step` / `2edn7534fxtma1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590284255428849664) (36 pp, sha256 `e08bf597f6c026a0`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/2edn7534fxtma1-datasheet.pdf)