# 2EDN7534BXTSA1

**Infineon Technologies** · Gate Drivers · SOT-23-6

2EDN7534BXTSA1 from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTB | output | Driver output channel B is a low-impedance output with source and sink capability. |
| 2 | GND | power_in | Gate driver reference ground. |
| 3 | OUTA | output | Driver output channel A is a low-impedance output with source and sink capability. |
| 4 | INA | input | Logic input controlling OUTA in non-inverting configuration. |
| 5 | INB | input | Logic input controlling OUTB in non-inverting configuration. |
| 6 | VDD | power_in | Positive supply voltage with an operating range of 4.5 V to 20 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Motor Driver ICs |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VDD | -0.3 |  | 22 | V |  | 13 |
| Voltage at pins INA, INB, ENA, ENB | VIN | -12 |  | 22 | V |  | 13 |
| Voltage at pins OUTA, OUTB | VOUT | -0.3 |  |  | V | Max VDD+0.3 V; note 1: voltage spikes from reverse current peaks allowed | 13 |
| Voltage at pins OUTA, OUTB (repetitive pulse) | VOUT | -2 |  |  | V | Max VDD+2 V; repetitive pulse < 200 ns | 13 |
| Reverse current peak at pins OUTA, OUTB | ISNKREV, ISRCREV | -5 |  | 5 | A | Apk < 500 ns | 13 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 13 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 13 |
| ESD capability (CDM) | VESD |  |  | 0.5 | kV | Charged Device Model (CDM), per JESD22-002 | 13 |
| ESD capability (HBM) | VESD |  |  | 2 | kV | Human Body Model (HBM), per JESD22-A114-B | 13 |
| Thermal resistance junction-ambient | RthJA25 |  | 163 |  | K/W | PG-SOT23-6, Tamb=25°C | 14 |
| Thermal resistance junction-case (top) | RthJC25 |  | 69 |  | K/W | PG-SOT23-6, Tamb=25°C | 14 |
| Thermal resistance junction-board | RthJB25 |  | 36 |  | K/W | PG-SOT23-6, Tamb=25°C | 14 |
| Characterization parameter junction-case (top) | ΨthJC25 |  | 13 |  | K/W | PG-SOT23-6, Tamb=25°C | 14 |
| Characterization parameter junction-board | ΨthJB25 |  | 36 |  | K/W | PG-SOT23-6, Tamb=25°C | 14 |
| Supply voltage | VDD | 4.5 |  | 20 | V | Min. defined by UVLO | 15 |
| Logic input voltage | VIN | -10 |  | 20 | V |  | 15 |
| Junction temperature (operating) | TJ | -40 |  | 150 | °C |  | 15 |
| VDD quiescent current (output high) | IVDDQU1 | 0.5 | 0.9 | 1.2 | mA | OUT = high, VDD = 12 V | 15 |
| VDD quiescent current (output low) | IVDDQU2 | 0.3 | 0.5 | 0.7 | mA | OUT = low, VDD = 12 V | 15 |
| UVLO turn-on threshold (4 V version) | UVLOON |  | 4.2 | 4.5 | V |  | 15 |
| UVLO turn-off threshold (4 V version) | UVLOOFF | 3.6 | 3.9 |  | V |  | 15 |
| UVLO threshold hysteresis (4 V version) | UVLOHYS | 0.25 | 0.3 | 0.35 | V |  | 15 |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V |  | 16 |
| Input voltage threshold for transition HL | VINL | 1 | 1.2 | 1.4 | V |  | 16 |
| High level (sourcing) output resistance (2EDN753x) | RONSRC | 0.4 | 0.8 | 1.4 | Ω | ISRC = 50 mA | 16 |
| Low level (sinking) output resistance (2EDN753x) | RONSNK | 0.35 | 0.6 | 1.2 | Ω | ISNK = 50 mA | 16 |
| Input/Enable to output propagation delay, low to high | tPDlh | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable | 17 |
| Input/Enable to output propagation delay, high to low | tPDhl | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VDD= 12 V; high to low transition at Input/Enable | 17 |
| Propagation delay mismatch between the two channels on the same IC | ∆tPD |  |  | 2 | ns |  | 17 |
| Rise time | tRISE |  | 8.6 | 15 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 |
| Fall time | tFALL |  | 6 | 13 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 |
| Minimum input pulse width that changes output state | tPW |  | 6 | 10 | ns | CLOAD = 1.8 nF, VDD = 12 V | 17 |

## CAD (KiCad official)

- Symbol: `2EDN7534BXTSA1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `2edn7534bxtsa1-etched.step` / `2edn7534bxtsa1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `2edn7534bxtsa1.step` / `2edn7534bxtsa1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590890272816001024) (36 pp, sha256 `68b2a319c01dcd93`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/2edn7534bxtsa1-datasheet.pdf)