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2EDN7533BXTSA1

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Infineon Technologies Gate Drive ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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2EDN7533BXTSA1

Infineon Technologies · Gate Drive ICs · SOT-23-6

2EDN7533BXTSA1 from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUTB output Driver output channel B, a low-impedance output with source and sink capability.
2 GND power_in Ground, gate driver reference ground.
3 OUTA output Driver output channel A, a low-impedance output with source and sink capability.
4 INA input Input signal channel A, logic input controlling OUTA (inverting for 2EDN7533B, per the logic table on page 3).
5 INB input Input signal channel B, logic input controlling OUTB (inverting for 2EDN7533B, per the logic table on page 3).
6 VDD power_in Positive supply voltage with an operating range of 4.5 V to 20 V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOT-23-6
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive supply voltage VDD -0.3 22 V 13
Voltage at pins INA, INB, ENA, ENB VIN -12 22 V 13
Voltage at pins OUTA, OUTB (repetitive pulse) VOUT -2 V Repetitive pulse < 200 ns; max printed as VDD+2 V 13
Reverse current peak at pins OUTA, OUTB ISNKREV/ISRCREV -5 5 Apk < 500 ns 13
Junction temperature TJ -40 150 °C 13
Storage temperature TS -55 150 °C 13
ESD capability CDM VESD 0.5 kV Charged Device Model (CDM) 13
ESD capability HBM VESD 2 kV Human Body Model (HBM) 13
Supply voltage VDD 4.5 20 V Min. defined by UVLO 15
Logic input voltage VIN -10 20 V 15
Junction temperature TJ -40 150 °C Continuous operation above 125°C may reduce life time 15
VDD quiescent current IVDDQU1 0.5 0.9 1.2 mA OUT = high, VDD = 12 V 15
VDD quiescent current IVDDQU2 0.3 0.5 0.7 mA OUT = low, VDD = 12 V 15
UVLO turn on threshold UVLOON 4.2 4.5 V 15
UVLO turn off threshold UVLOOFF 3.6 3.9 V 15
UVLO threshold hysteresis UVLOHYS 0.25 0.3 0.35 V 15
Input voltage threshold for transition LH VINH 1.9 2.1 2.3 V 16
Input voltage threshold for transition HL VINL 1 1.2 1.4 V 16
High level (sourcing) output resistance RONSRC 0.4 0.8 1.4 Ω ISRC = 50 mA 16
Low level (sinking) output resistance RONSNK 0.35 0.6 1.2 Ω ISNK = 50 mA 16
Input/Enable to output propagation delay tPDlh 15 19 25 ns CLOAD= 1.8 nF, VDD= 12 V; low to high transition at Input/Enable 17
Propagation delay mismatch between the two channels ∆tPD 2 ns 17
Rise time tRISE 8.6 15 ns CLOAD = 1.8 nF, VDD = 12 V 17
Fall time tFAll 6 13 ns CLOAD = 1.8 nF, VDD = 12 V 17
Minimum input pulse width that changes output state tPW 6 10 ns CLOAD = 1.8 nF, VDD = 12 V 17
Input pull up resistor RINH 400 kΩ Inputs with initial high logic level 16
Input pull down resistor RINL 100 kΩ Inputs with initial low logic level 16
High level (sourcing) output current ISRCPEAK 5 A 16
Low level (sinking) output current ISNKPEAK -5 A 16
VDD start-up time from UVLOON to OUTx tSTART 1.8 µs VDD rising to 12 V; see Figure 11 17
VDD deactivation time from UVLOOFF to OUTx tSTOP 500 ns VDD falling from 12 V; see Figure 11 17
Activation time of output clamping in UVLO condition tCLAMP,OUT 20 ns see Figure 13 17
Thermal resistance junction-ambient, PG-SOT23-6 RthJA25 163 K/W Tamb = 25°C 14
Thermal resistance junction-case (top), PG-SOT23-6 RthJC25 69 K/W Tamb = 25°C 14
Thermal resistance junction-board, PG-SOT23-6 RthJB25 36 K/W Tamb = 25°C 14
Characterization parameter junction-case (top), PG-SOT23-6 ΨthJC25 13 K/W Tamb = 25°C 14
Characterization parameter junction-board, PG-SOT23-6 ΨthJB25 36 K/W Tamb = 25°C 14

CAD (KiCad official)

  • Symbol: 2EDN7533BXTSA1
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: 2edn7533bxtsa1-etched.step / 2edn7533bxtsa1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2edn7533bxtsa1.step / 2edn7533bxtsa1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (36 pp, sha256 1211e0b01e1395b1, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF