# 25LC640T-E

**Microchip Tech** · EEPROM · SOIC-8

25LC640T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and a low-to-high transition after a valid write sequence starts the internal write cycle. |
| 2 | SO | tri_state | Serial data output that shifts data out after the falling edge of SCK during reads and goes to the high-impedance state when the device is deselected or HOLD is pulled low. |
| 3 | WP | input | Write-protect input that, when low while WPEN is high, disables writes to the nonvolatile bits in the STATUS register; the pin is blocked when WPEN is low. |
| 4 | VSS | power_in | Ground reference for the device; all inputs and outputs are specified with respect to VSS. |
| 5 | SI | input | Serial data input that receives instructions, addresses and data, latched on the rising edge of SCK. |
| 6 | SCK | input | Serial clock input; SI is latched on its rising edge and SO is updated after its falling edge. |
| 7 | HOLD | input | Hold input that pauses serial communication when pulled low while SCK is low, must be held high when unused, and tri-states SO when lowered. |
| 8 | VCC | power_in | Supply voltage; absolute maximum VCC is 7.0 V and the 25LC640 is specified at 2.5 V to 5.5 V (4.5 V to 5.5 V for the 3 MHz / 2.5 MHz rating). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input low-level voltage (VIL1) | VIL1 | -0.3 |  | 0.8 | V | VCC ≥ 2.7V (Note 1) | 2 |
| Input high-level voltage (VIH1) | VIH1 | 2 |  |  | V | VCC ≥ 2.7V (Note 1); printed max is VCC + 1 V, not numeric | 2 |
| Low-level output voltage | VOL |  |  | 0.4 | V | IOL = 2.1 mA | 2 |
| Input leakage current | ILI | -1 |  | 1 | μA | CS = VCC, VIN = VSS TO VCC | 2 |
| Output leakage current | ILO | -1 |  | 1 | μA | CS = VCC, VOUT = VSS TO VCC | 2 |
| Internal capacitance (all inputs and outputs) | CINT |  |  | 7 | pF | TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) | 2 |
| Read operating current | ICC |  |  | 1 | mA | VCC = 5.5V; FCLK = 3.0 MHz; SO = Open | 2 |
| Write operating current | ICC |  |  | 5 | mA | VCC = 5.5V | 2 |
| Standby current | ICCS |  |  | 5 | μA | CS = VCC = 5.5V, Inputs tied to VCC or VSS | 2 |
| Clock frequency | FCLK |  |  | 3 | MHz | VCC = 4.5V to 5.5V (Note 2) | 3 |
| CS setup time | TCSS | 100 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| CS hold time | TCSH | 150 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| CS disable time | TCSD | 500 |  |  | ns |  | 3 |
| Data setup time | TSU | 30 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| Data hold time | THD | 50 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| CLK rise time | TR |  |  | 2 | μs | (Note 1) | 3 |
| CLK fall time | TF |  |  | 2 | μs | (Note 1) | 3 |
| Clock high time | THI | 150 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| Clock low time | TLO | 150 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| Clock delay time | TCLD | 50 |  |  | ns |  | 3 |
| Clock enable time | TCLE | 50 |  |  | ns |  | 3 |
| Output valid from clock low | TV |  |  | 150 | ns | VCC = 4.5V to 5.5V | 3 |
| Output hold time | THO | 0 |  |  | ns | (Note 1) | 3 |
| Output disable time | TDIS |  |  | 200 | ns | VCC = 4.5V to 5.5V (Note 1) | 3 |
| HOLD setup time | THS | 100 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| HOLD hold time | THH | 100 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| HOLD low to output high-Z | THZ | 100 |  |  | ns | VCC = 4.5V to 5.5V (Note 1) | 3 |
| HOLD high to output valid | THV | 100 |  |  | ns | VCC = 4.5V to 5.5V | 3 |
| Internal write cycle time | TWC |  |  | 5 | ms |  | 3 |
| Supply voltage VCC (E grade operating range) | VCC | 4.5 |  | 5.5 | V | Automotive (E) grade, TA = -40°C to +125°C | 2 |
| Ambient temperature range (E grade) | TA | -40 |  | 125 | °C | Automotive (E), VCC = 4.5V to 5.5V | 2 |
| VCC supply voltage (absolute maximum) | VCC |  |  | 7 | V |  | 2 |
| Voltage on all inputs and outputs w.r.t. VSS (minimum) |  | -0.6 |  |  | V | printed max is VCC + 1.0 V, not numeric | 2 |
| Storage temperature |  | -65 |  | 150 | °C |  | 2 |
| Ambient temperature under bias |  | -65 |  | 125 | °C |  | 2 |
| ESD protection on all pins |  |  |  | 4 | kV |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Package P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead | 21 |

## CAD (KiCad official)

- Symbol: `25LC640T-E`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `25lc640t-e-etched.step` / `25lc640t-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `25lc640t-e.step` / `25lc640t-e.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/25lc640t-e-datasheet.pdf) (24 pp, sha256 `6c8e98edc6deaaf3`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/25lc640t-e-datasheet.pdf)