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25LC512-I

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Microchip Tech EEPROM, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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25LC512-I

Microchip Tech · EEPROM · PDIP-8

25LC512-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input A low level selects the device and a high level deselects it and forces Standby mode, but an already initiated program cycle completes regardless of CS; a low-to-high transition after a valid write sequence starts the internal write cycle.
2 SO output Serial data output that shifts data out after the falling edge of SCK during a read, and goes to the high-impedance state when the device is deselected.
3 WP input With the WPEN bit set in the STATUS register, WP low prohibits writes to the nonvolatile STATUS register bits; the WP function is blocked when WPEN is low.
4 VSS power_in Ground reference for the device.
5 SI input Serial data input that receives instructions, addresses and data, latched on the rising edge of SCK.
6 SCK input Serial clock that synchronizes communication: SI is latched on its rising edge and SO is updated after its falling edge.
7 HOLD input Pauses serial communication while the device is selected mid-sequence when driven low (best done while SCK is low), and must be held high when the function is not used.
8 VCC power_in Supply voltage, specified at 2.5V to 5.5V with absolute maximum VCC of 6.5V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
All inputs and outputs w.r.t. VSS -0.6 V 2
Storage temperature -65 150 °C 2
Ambient temperature under bias -40 125 °C 2
Supply voltage VCC 2.5 5.5 V DC characteristics, Industrial (I) and Automotive (E) 2
Ambient temperature TA -40 85 °C Industrial (I) 2
Low-level input voltage VIL1 -0.3 V VCC ≥ 2.7V 2
Low-level output voltage VOL 0.4 V IOL = 2.1 mA 2
Input leakage current ILI -1 1 µA CS = VCC, VIN = VSS or VCC 2
Output leakage current ILO -1 1 µA CS = VCC, VOUT = VSS or VCC 2
Internal capacitance (all inputs and outputs) CINT 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) 2
Read operating current ICC 10 mA VCC = 5.5V; FCLK = 20.0 MHz; SO = Open 2
Read operating current ICC 5 mA VCC = 2.5V; FCLK = 10.0 MHz; SO = Open 2
Write operating current ICC 7 mA VCC = 5.5V 2
Write operating current ICC 5 mA VCC = 2.5V 2
Standby current ICCS 10 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C 2
Deep power-down current ICCSPD 1 µA CS = VCC = 2.5V, Inputs tied to VCC or VSS, 85°C 2
Clock frequency FCLK 20 MHz 4.5V ≤ VCC ≤ 5.5V (I) 3
Clock frequency FCLK 10 MHz 2.5V ≤ VCC ≤ 5.5V (I, E) 3
CS setup time TCSS 25 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
CS setup time TCSS 50 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
CS hold time TCSH 50 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
CS hold time TCSH 100 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
CS disable time TCSD 50 ns 3
Data setup time Tsu 5 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Data setup time Tsu 10 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
Data hold time THD 10 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Data hold time THD 20 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
CLK rise time TR 20 ns (Note 1) 3
CLK fall time TF 20 ns (Note 1) 3
Clock high time THI 25 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Clock high time THI 50 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
Clock low time TLO 25 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Clock low time TLO 50 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
Clock delay time TCLD 50 ns 3
Clock enable time TCLE 50 ns 3
Output valid from clock low TV 25 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Output valid from clock low TV 50 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
Output hold time THO 0 ns (Note 1) 3
Output disable time TDIS 25 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
Output disable time TDIS 50 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
HOLD setup time THS 10 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
HOLD setup time THS 20 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
HOLD hold time THH 10 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
HOLD hold time THH 20 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
HOLD low to output High-Z THZ 15 ns 4.5V ≤ VCC ≤ 5.5V (I) (Note 1) 3
HOLD low to output High-Z THZ 30 ns 2.5V ≤ VCC ≤ 5.5V (I, E) (Note 1) 3
HOLD high to output valid THV 15 ns 4.5V ≤ VCC ≤ 5.5V (I) 3
HOLD high to output valid THV 30 ns 2.5V ≤ VCC ≤ 5.5V (I, E) 3
CS High to Standby mode TREL 100 µs 3
CS High to Deep power-down TPD 100 µs 3
Chip erase cycle time TCE 10 ms 3
Sector erase cycle time TSE 10 ms 3
Internal write cycle time TWC 5 ms Byte or Page mode and Page Erase 3

CAD (KiCad official)

  • Symbol: 25LC512-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: 25lc512-i-etched.step / 25lc512-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25lc512-i.step / 25lc512-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 f03deca2f12a418b, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF