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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

25LC256

Microchip Technology · 256 Kbit SPI EEPROM · SOIC-8

A 256 Kbit (32 KB) serial EEPROM with an SPI interface, in SOIC-8, the SPI counterpart of the I2C 24LC256. It stores settings, calibration, and logs that must survive power loss, with a rated endurance over one million erase/write cycles and data retention beyond 200 years. Data is written a byte or a 64-byte page at a time and read sequentially at up to 10 MHz over the four-wire SPI. A hardware write-protect pin plus block-protect bits guard part or all of the array against accidental writes, and a HOLD pin pauses a transfer without dropping chip select. Runs 1.8-5.5 V.

Pinout

Pin	Name	Type	Function
1	CS	input	Chip Select input (active-low, overbar CS). Drive low to select the device and initiate an SPI instruction; drive high to deselect and place SO in high-impedance. Requires TCSS setup (≥50 ns @ Vcc≥4.5 V) before the first SCK edge.
2	SO	output	Serial Data Output (MISO). Shifts data out on the falling edge of SCK, MSB first. High-impedance when CS is high or HOLD is low. Drive strength: VOH = Vcc-0.5 V @ IOH = -400 µA.
3	WP	input	Write-Protect input (active-low, overbar WP). When low and the WPEN bit in the status register is set, prevents writes to the status register (hardware write-protect). Tie high (or leave floating with pull-up) for normal operation.
4	VSS	power_in	Ground reference for all supply, logic, and I/O signals. Connect to system 0 V.
5	SI	input	Serial Data Input (MOSI). Command bytes, addresses, and write data are shifted in on the rising edge of SCK, MSB first. Data setup Tsu ≥ 10 ns @ Vcc ≥ 4.5 V.
6	SCK	input	Serial Clock Input. Provides the clock for all serial data transfers on SI/SO. Maximum 10 MHz @ Vcc ≥ 4.5 V (5 MHz @ 2.5-4.5 V, 3 MHz @ 1.8-2.5 V for 25AA256). Supports SPI Mode 0,0 and Mode 1,1.
7	HOLD	input	Hold input (active-low, overbar HOLD). Drive low to pause the current SPI transaction while CS remains asserted; SO goes high-impedance and SI/SCK transitions are ignored. Drive high to resume. Tie high if not used.
8	VCC	power_in	Supply voltage input. 2.5-5.5 V for 25LC256 (1.8-5.5 V for 25AA256). Absolute max 6.5 V. Typical operating current 2.5 mA read / 0.6 mA write @ 5.5 V; standby 0.1 µA typ. Decouple with 0.1 µF close to the pin.

Key specifications

Parameter	Value
Type	Serial EEPROM (non-volatile)
Density	256 Kbit (32 KB)
Interface	SPI (up to 10 MHz)
Write	byte or 64-byte page
Endurance	1,000,000+ cycles
Retention	>200 years
Protection	WP pin + block-protect bits
Supply voltage	1.8-5.5 V
Package	SOIC-8

Ordering variants

25LC256-I/SN (SOIC-8)
25LC256-I/P (PDIP-8)

CAD (KiCad official)

Symbol: Memory_EEPROM:25LCxxx
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D)
3D model files: 25lc256-etched.step / 25lc256-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25lc256.step / 25lc256.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Technology datasheet (31 pp, sha256 b25667250a0ee8d3, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF