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25LC160DT-I

Microchip Tech · EEPROM · SOIC-8

25LC160DT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select input: a low level selects the device, while a high level deselects it and forces it into Standby mode.
2 SO output Serial Data Output: data is shifted out after the falling edge of SCK during a read, and SO goes to the high-impedance state when the device is deselected.
3 WP input Write-Protect input that, when WPEN is set and WP is low, disables writes to the nonvolatile bits in the STATUS register; it has no effect on an internal write cycle already in progress.
4 VSS power_in Ground reference for the device.
5 SI input Serial Data Input: receives instructions, addresses and data, latched on the rising edge of the serial clock.
6 SCK input Serial Clock input that synchronizes communication; SI is latched on its rising edge and SO updates after its falling edge.
7 HOLD input Active-low HOLD input that pauses serial communication without resetting the sequence; it must be held high when unused and brought low while SCK is low.
8 VCC power_in Supply voltage; the 25LC160D is specified for a VCC range of 2.5-5.5V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-level input voltage VIL1 -0.3 V VCC ≥ 2.7V 2
Low-level input voltage VIL1 0.3 VCC VCC ≥ 2.7V 2
Low-level input voltage (VCC < 2.7V) VIL2 -0.3 V VCC < 2.7V 2
Low-level input voltage (VCC < 2.7V) VIL2 0.2 VCC VCC < 2.7V 2
Low-level output voltage VOL1 0.4 V IOL = 2.1 mA 2
High-level output voltage (printed VCC-0.5) VOH -0.5 V rel. VCC IOH = -400 µA 2
Input leakage current ILI -1 1 µA CS = VCC, VIN = VSS OR VCC 2
Output leakage current ILO -1 1 µA CS = VCC, VOUT = VSS OR VCC 2
Internal capacitance (all inputs and outputs) CINT 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) 2
Read operating current ICC 5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open 2
Read operating current ICC 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open 2
Write operating current ICC 5 mA VCC = 5.5V 2
Write operating current ICC 3 mA VCC = 2.5V 2
Standby current (Industrial, +85°C) ICCS 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +85°C 2
Clock frequency FCLK 10 MHz 4.5V ≤ VCC ≤ 5.5V 3
Clock frequency FCLK 5 MHz 2.5V ≤ VCC ≤ 4.5V 3
CS setup time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 3
CS setup time TCSS 100 ns 2.5V ≤ VCC ≤ 4.5V 3
CS hold time TCSH 100 ns 4.5V ≤ VCC ≤ 5.5V 3
CS hold time TCSH 200 ns 2.5V ≤ VCC ≤ 4.5V 3
CS disable time TCSD 50 ns 3
Data setup time Tsu 10 ns 4.5V ≤ VCC ≤ 5.5V 3
Data setup time Tsu 20 ns 2.5V ≤ VCC ≤ 4.5V 3
Data hold time THD 20 ns 4.5V ≤ VCC ≤ 5.5V 3
Data hold time THD 40 ns 2.5V ≤ VCC ≤ 4.5V 3
CLK rise time TR 2 µs (Note 1) 3
CLK fall time TF 2 µs (Note 1) 3
Clock high time THI 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock high time THI 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock low time TLO 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock low time TLO 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock delay time TCLD 50 ns 3
Clock enable time TCLE 50 ns 3
Output valid from clock low TV 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Output valid from clock low TV 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Output hold time THO 0 ns (Note 1) 3
Output disable time TDIS 40 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 3
Output disable time TDIS 80 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 3
HOLD setup time THS 20 ns 4.5V ≤ VCC ≤ 5.5V 3
HOLD setup time THS 40 ns 2.5V ≤ VCC ≤ 4.5V 3
HOLD hold time THH 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD hold time THH 40 ns 2.5V ≤ VCC ≤ 4.5V 4
HOLD low to output high-Z THZ 30 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
HOLD low to output high-Z THZ 60 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 4
HOLD high to output valid THV 30 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD high to output valid THV 60 ns 2.5V ≤ VCC ≤ 4.5V 4
Internal write cycle time TWC 5 ms (Note 2) 4
Endurance 1 M E/W cycles 25°C, VCC = 5.5V (Note 3) 4
Data retention 200 years 1
Supply voltage range (25LC160D) VCC 2.5 5.5 V 1
Ambient temperature, Industrial (I) TA -40 85 °C 2
Voltage on all inputs and outputs w.r.t. VSS (lower limit) -0.6 V 2
Storage temperature -65 150 °C 2
Ambient temperature under bias -40 125 °C 2
ESD protection on all pins 4 kV 2

CAD (KiCad official)

  • Symbol: 25LC160DT-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 25lc160dt-i-etched.step / 25lc160dt-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25lc160dt-i.step / 25lc160dt-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (34 pp, sha256 3197ea7d4ba05bfd, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF