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25LC160C-I

Microchip Tech · Pre-ordered Chips · PDIP-8

25LC160C-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and a low-to-high transition after a valid write sequence starts an internal write cycle.
2 SO tri_state Serial data output that shifts data out after the falling edge of SCK and goes to the high-impedance state when the device is deselected.
3 WP input Write-protect pin that, together with the WPEN STATUS register bit, disables writes to the nonvolatile STATUS register bits when low and has no effect on a write cycle already in progress.
4 VSS power_in Ground reference pin for the device.
5 SI input Serial data input that receives instructions, addresses and data, latched on the rising edge of SCK.
6 SCK input Serial clock input that synchronizes communication; SI is latched on its rising edge and SO updates after its falling edge.
7 HOLD input Hold input that pauses serial communication when pulled low while SCK is low, must be held high when unused, and tri-states SO when lowered.
8 VCC power_in Supply voltage pin; for the 25LC160C it is 2.5-5.5V per the device selection table.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Clock Frequency FCLK 10 MHz 4.5V ≤ VCC ≤ 5.5V 3
Clock Frequency FCLK 5 MHz 2.5V ≤ VCC ≤ 4.5V 3
CS Setup Time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Setup Time TCSS 100 ns 2.5V ≤ VCC ≤ 4.5V 3
CS Hold Time TCSH 100 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Hold Time TCSH 200 ns 2.5V ≤ VCC ≤ 4.5V 3
CS Disable Time TCSD 50 ns 3
Data Setup Time Tsu 10 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Setup Time Tsu 20 ns 2.5V ≤ VCC ≤ 4.5V 3
Data Hold Time THD 20 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Hold Time THD 40 ns 2.5V ≤ VCC ≤ 4.5V 3
CLK Rise Time TR 2 µs (Note 1) 3
CLK Fall Time TF 2 µs (Note 1) 3
Clock High Time THI 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock High Time THI 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock Low Time TLO 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock Low Time TLO 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock Delay Time TCLD 50 ns 3
Clock Enable Time TCLE 50 ns 3
Output Valid from Clock Low TV 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Output Valid from Clock Low TV 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Output Hold Time THO 0 ns (Note 1) 3
Output Disable Time TDIS 40 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 3
Output Disable Time TDIS 80 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 3
HOLD Setup Time THS 20 ns 4.5V ≤ VCC ≤ 5.5V 3
HOLD Setup Time THS 40 ns 2.5V ≤ VCC ≤ 4.5V 3
HOLD Hold Time THH 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD Hold Time THH 40 ns 2.5V ≤ VCC ≤ 4.5V 4
HOLD Low to Output High-Z THZ 30 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
HOLD Low to Output High-Z THZ 60 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 4
HOLD High to Output Valid THV 30 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD High to Output Valid THV 60 ns 2.5V ≤ VCC ≤ 4.5V 4
Internal Write Cycle Time TWC 5 ms (Note 2) 4
Endurance 1 M E/W cycles 25°C, VCC = 5.5V (Note 3) 4
Low-level input voltage VIL1 -0.3 V VCC ≥ 2.7V 2
Low-level output voltage VOL1 0.4 V IOL = 2.1 mA 2
Input leakage current ILI -1 1 µA CS = VCC, VIN = VSS OR VCC 2
Output leakage current ILO -1 1 µA CS = VCC, VOUT = VSS OR VCC 2
Internal Capacitance (all inputs and outputs) CINT 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) 2
Read Operating Current ICC 5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open 2
Read Operating Current ICC 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open 2
Write Operating Current ICC 5 mA VCC = 5.5V 2
Write Operating Current ICC 3 mA VCC = 2.5V 2
Standby Current ICCS 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +85°C 2
Supply voltage VCC 2.5 5.5 V 25LC160C VCC range (Device Selection Table) 1
Ambient temperature, Industrial (I) TA -40 85 °C Industrial (I) grade 1
Voltage on any input or output pin w.r.t. VSS -0.6 V 2
Storage temperature -65 150 °C 2
Ambient temperature under bias -40 125 °C under bias 2
ESD protection on all pins 4 kV 2

CAD (KiCad official)

  • Symbol: 25LC160C-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: 25lc160c-i-etched.step / 25lc160c-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25lc160c-i.step / 25lc160c-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (34 pp, sha256 3197ea7d4ba05bfd, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF