component
25LC080AT-I
Public Made by Adomby adom
Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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25LC080AT-I
Microchip Tech · EEPROM · SOIC-8
25LC080AT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, and a high level deselects it and forces Standby mode while SO goes high-impedance. |
| 2 | SO | output | Serial Data Output: data shifts out after the falling edge of SCK, and the pin is tri-stated when the device is deselected or HOLD is pulled low. |
| 3 | WP | input | Write-Protect input: with WPEN set, a low level disables writes to the nonvolatile Status Register bits, and the pin has no effect when WPEN is low. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SI | input | Serial Data Input: instructions, addresses and data are latched on the rising edge of SCK, and transitions are ignored while HOLD pauses the device. |
| 6 | SCK | input | Serial Clock input: SI is latched on its rising edge and SO updates after its falling edge. |
| 7 | HOLD | input | Hold input: must be held high when unused; pulling it low while SCK is low pauses serial communication without resetting the sequence and tri-states SO. |
| 8 | VCC | power_in | Supply voltage: 2.5V to 5.5V for the 25LC080A per the device selection table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH1 | 2 | V | VCC ≥ 2.7V (Note) | 2 | ||
| Low-level input voltage | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V (Note) | 2 | |
| Low-level input voltage | VIL2 | -0.3 | V | VCC < 2.7V (Note) | 2 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 2.1 mA | 2 | ||
| Input leakage current | ILI | -1 | 1 | μA | CS = VCC, VIN = VSS TO VCC | 2 | |
| Output leakage current | ILO | -1 | 1 | μA | CS = VCC, VOUT = VSS TO VCC | 2 | |
| Internal Capacitance (all inputs and outputs) | CINT | 7 | pF | TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) | 2 | ||
| Read Operating Current | ICC | 6 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 | ||
| Read Operating Current | ICC | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 | ||
| Write Operating Current | ICC | 3 | mA | VCC = 5.5V | 2 | ||
| Standby Current | Iccs | 1 | μA | CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C | 2 | ||
| Clock Frequency | FCLK | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock Frequency | FCLK | 5 | MHz | 2.5V ≤ VCC < 4.5V | 3 | ||
| CS Setup Time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS Setup Time | TCSS | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| CS Hold Time | TCSH | 100 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS Hold Time | TCSH | 200 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| CS Disable Time | TCSD | 50 | ns | 3 | |||
| Data Setup Time | Tsu | 10 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data Setup Time | Tsu | 20 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Data Hold Time | THD | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data Hold Time | THD | 40 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| CLK Rise Time | TR | 500 | ns | (Note 1) | 3 | ||
| CLK Fall Time | TF | 500 | ns | (Note 1) | 3 | ||
| Clock High Time | THI | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock High Time | THI | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Clock Low Time | TLO | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock Low Time | TLO | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Clock Delay Time | TCLD | 50 | ns | 3 | |||
| Clock Enable Time | TCLE | 50 | ns | 3 | |||
| Output Valid from Clock Low | TV | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Output Valid from Clock Low | TV | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| Output Hold Time | THO | 0 | ns | (Note 1) | 3 | ||
| Output Disable Time | TDIS | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 | ||
| Output Disable Time | TDIS | 80 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 3 | ||
| HOLD Setup Time | THS | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| HOLD Setup Time | THS | 40 | ns | 2.5V ≤ VCC < 4.5V | 3 | ||
| HOLD Hold Time | THH | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD Hold Time | THH | 40 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| HOLD Low to Output High-Z | THZ | 30 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 | ||
| HOLD Low to Output High-Z | THZ | 60 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 | ||
| HOLD High to Output Valid | THV | 30 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD High to Output Valid | THV | 60 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| Internal Write Cycle Time | TWC | 5 | ms | (Note 3) | 4 | ||
| Endurance | 1e+06 | E/W cycles | 4 | ||||
| Supply voltage VCC (25LC080A) | VCC | 2.5 | 5.5 | V | 25LC080A VCC range | 1 | |
| Ambient temperature, Industrial (I) | TAMB | -40 | 85 | °C | Industrial (I) grade | 1 | |
| Supply voltage VCC | VCC | 7 | V | 2 | |||
| Input/output voltage w.r.t. VSS | -0.6 | V | w.r.t. VSS; upper limit printed as VCC +1.0V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature under bias | -65 | 125 | °C | 2 | |||
| ESD protection on all pins | 4 | kV | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN or OA), Narrow, 3.90 mm Body [SOIC] Notes: | 17 |
CAD (KiCad official)
- Symbol:
25LC080AT-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
25lc080at-i-etched.step/25lc080at-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);25lc080at-i.step/25lc080at-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (26 pp, sha256
31b8a647cd7c4b8e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 25LC080AT-I
**Microchip Tech** · EEPROM · SOIC-8
25LC080AT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, and a high level deselects it and forces Standby mode while SO goes high-impedance. |
| 2 | SO | output | Serial Data Output: data shifts out after the falling edge of SCK, and the pin is tri-stated when the device is deselected or HOLD is pulled low. |
| 3 | WP | input | Write-Protect input: with WPEN set, a low level disables writes to the nonvolatile Status Register bits, and the pin has no effect when WPEN is low. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SI | input | Serial Data Input: instructions, addresses and data are latched on the rising edge of SCK, and transitions are ignored while HOLD pauses the device. |
| 6 | SCK | input | Serial Clock input: SI is latched on its rising edge and SO updates after its falling edge. |
| 7 | HOLD | input | Hold input: must be held high when unused; pulling it low while SCK is low pauses serial communication without resetting the sequence and tri-states SO. |
| 8 | VCC | power_in | Supply voltage: 2.5V to 5.5V for the 25LC080A per the device selection table. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH1 | 2 | | | V | VCC ≥ 2.7V (Note) | 2 |
| Low-level input voltage | VIL1 | -0.3 | | 0.8 | V | VCC ≥ 2.7V (Note) | 2 |
| Low-level input voltage | VIL2 | -0.3 | | | V | VCC < 2.7V (Note) | 2 |
| Low-level output voltage | VOL | | | 0.4 | V | IOL = 2.1 mA | 2 |
| Input leakage current | ILI | -1 | | 1 | μA | CS = VCC, VIN = VSS TO VCC | 2 |
| Output leakage current | ILO | -1 | | 1 | μA | CS = VCC, VOUT = VSS TO VCC | 2 |
| Internal Capacitance (all inputs and outputs) | CINT | | | 7 | pF | TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) | 2 |
| Read Operating Current | ICC | | | 6 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 |
| Read Operating Current | ICC | | | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 |
| Write Operating Current | ICC | | | 3 | mA | VCC = 5.5V | 2 |
| Standby Current | Iccs | | | 1 | μA | CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C | 2 |
| Clock Frequency | FCLK | | | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock Frequency | FCLK | | | 5 | MHz | 2.5V ≤ VCC < 4.5V | 3 |
| CS Setup Time | TCSS | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS Setup Time | TCSS | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| CS Hold Time | TCSH | 100 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS Hold Time | TCSH | 200 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| CS Disable Time | TCSD | 50 | | | ns | | 3 |
| Data Setup Time | Tsu | 10 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data Setup Time | Tsu | 20 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Data Hold Time | THD | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data Hold Time | THD | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| CLK Rise Time | TR | | | 500 | ns | (Note 1) | 3 |
| CLK Fall Time | TF | | | 500 | ns | (Note 1) | 3 |
| Clock High Time | THI | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock High Time | THI | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Clock Low Time | TLO | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock Low Time | TLO | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Clock Delay Time | TCLD | 50 | | | ns | | 3 |
| Clock Enable Time | TCLE | 50 | | | ns | | 3 |
| Output Valid from Clock Low | TV | | | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Output Valid from Clock Low | TV | | | 100 | ns | 2.5V ≤ VCC < 4.5V | 3 |
| Output Hold Time | THO | 0 | | | ns | (Note 1) | 3 |
| Output Disable Time | TDIS | | | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 |
| Output Disable Time | TDIS | | | 80 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 3 |
| HOLD Setup Time | THS | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| HOLD Setup Time | THS | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 3 |
| HOLD Hold Time | THH | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD Hold Time | THH | 40 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| HOLD Low to Output High-Z | THZ | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 |
| HOLD Low to Output High-Z | THZ | 60 | | | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 |
| HOLD High to Output Valid | THV | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD High to Output Valid | THV | 60 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| Internal Write Cycle Time | TWC | | | 5 | ms | (Note 3) | 4 |
| Endurance | | 1e+06 | | | E/W cycles | | 4 |
| Supply voltage VCC (25LC080A) | VCC | 2.5 | | 5.5 | V | 25LC080A VCC range | 1 |
| Ambient temperature, Industrial (I) | TAMB | -40 | | 85 | °C | Industrial (I) grade | 1 |
| Supply voltage VCC | VCC | | | 7 | V | | 2 |
| Input/output voltage w.r.t. VSS | | -0.6 | | | V | w.r.t. VSS; upper limit printed as VCC +1.0V | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature under bias | | -65 | | 125 | °C | | 2 |
| ESD protection on all pins | | | | 4 | kV | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-Lead Plastic Small Outline (SN or OA), Narrow, 3.90 mm Body [SOIC] Notes: | 17 |
## CAD (KiCad official)
- Symbol: `25LC080AT-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `25lc080at-i-etched.step` / `25lc080at-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `25lc080at-i.step` / `25lc080at-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589830089166000128) (26 pp, sha256 `31b8a647cd7c4b8e`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/25lc080at-i-datasheet.pdf)