component
25AA640AT-I
Public Made by Adomby adom
Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
25AA640AT-I
Microchip Tech · Pre-ordered Chips · SOIC-8
25AA640AT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, and a high level deselects it and forces it into Standby mode, though a programming cycle already in progress will complete. |
| 2 | SO | output | Serial Data Output: data is shifted out after the falling edge of SCK during a read, and SO is high-impedance when the device is deselected or paused. |
| 3 | WP | input | Write-Protect: when WPEN is set, a low level on WP disables writes to the nonvolatile bits of the STATUS register, and the WP function is blocked when WPEN is low. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SI | input | Serial Data Input: receives instructions, addresses and data, which are latched on the rising edge of SCK. |
| 6 | SCK | input | Serial Clock input: SI is latched on its rising edge and SO is updated after its falling edge, synchronizing communication with the master. |
| 7 | HOLD | input | Hold input: must be held high when unused; pulling it low while SCK is low pauses serial communication and tri-states SO, and it must be brought high while SCK is low to resume. |
| 8 | VCC | power_in | Supply voltage; the 25AA640A is specified for 1.8V to 5.5V per the Device Selection Table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| All inputs and outputs w.r.t. VSS | -0.6 | 1 | V | Printed as -0.6V to VCC +1.0V; max entry is the +1.0V offset above VCC | 2 | ||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature under bias | -40 | 125 | °C | 2 | |||
| High-level input voltage (min 0.7 VCC; max VCC +1) | VIH1 | 0.7 | 1 | V (min = 0.7 × VCC; max = VCC + 1 V) | 2 | ||
| Low-level input voltage (max 0.3 VCC) | VIL1 | -0.3 | 0.3 | V (min -0.3 V; max = 0.3 × VCC) | VCC ≥ 2.7V | 2 | |
| Low-level input voltage (max 0.2 VCC) | VIL2 | -0.3 | 0.2 | V (min -0.3 V; max = 0.2 × VCC) | VCC < 2.7V | 2 | |
| Low-level output voltage | VOL | 0.4 | V | IOL = 2.1 mA | 2 | ||
| Low-level output voltage (low VCC) | VOL | 0.2 | V | IOL = 1.0 mA, VCC < 2.5V | 2 | ||
| High-level output voltage (min VCC -0.5) | VOH | -0.5 | V (min = VCC − 0.5 V) | IOH = -400 µA | 2 | ||
| Input leakage current | ILI | -1 | 1 | µA | CS = VCC, VIN = VSS or VCC | 2 | |
| Output leakage current | ILO | -1 | 1 | µA | CS = VCC, VOUT = VSS or VCC | 2 | |
| Read operating current | ICC | 5 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 | ||
| Read operating current | ICC | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 | ||
| Write operating current | ICC | 5 | mA | VCC = 5.5V | 2 | ||
| Write operating current | ICC | 3 | mA | VCC = 2.5V | 2 | ||
| Standby current (85°C) | ICCS | 1 | µA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C | 2 | ||
| Clock frequency (4.5V to 5.5V) | FCLK | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock frequency (2.5V to 4.5V) | FCLK | 5 | MHz | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Clock frequency (1.8V to 2.5V) | FCLK | 3 | MHz | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| CS setup time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS setup time | TCSS | 100 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| CS setup time | TCSS | 150 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| CS hold time | TCSH | 100 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| CS hold time | TCSH | 200 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| CS hold time | TCSH | 250 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| CS disable time | TCSD | 50 | ns | 3 | |||
| Data setup time | Tsu | 10 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data setup time | Tsu | 20 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Data setup time | Tsu | 30 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| Data hold time | THD | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Data hold time | THD | 40 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Data hold time | THD | 50 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| CLK rise time | TR | 100 | ns | (Note 1) | 3 | ||
| CLK fall time | TF | 100 | ns | (Note 1) | 3 | ||
| Clock high time | THI | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock high time | THI | 100 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Clock high time | THI | 150 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| Clock low time | TLO | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Clock low time | TLO | 100 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Clock low time | TLO | 150 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| Output valid from clock low | TV | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Output valid from clock low | TV | 100 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| Output valid from clock low | TV | 160 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| Output disable time | TDIS | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 | ||
| Output disable time | TDIS | 80 | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 3 | ||
| Output disable time | TDIS | 160 | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 3 | ||
| HOLD setup time | THS | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| HOLD setup time | THS | 40 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 | ||
| HOLD setup time | THS | 80 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 | ||
| HOLD hold time | THH | 20 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD hold time | THH | 40 | ns | 2.5V ≤ VCC ≤ 4.5V | 4 | ||
| HOLD hold time | THH | 80 | ns | 1.8V ≤ VCC ≤ 2.5V | 4 | ||
| HOLD low to output High-Z | THZ | 30 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 | ||
| HOLD low to output High-Z | THZ | 60 | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 4 | ||
| HOLD low to output High-Z | THZ | 160 | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 4 | ||
| HOLD high to output valid | THV | 30 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| HOLD high to output valid | THV | 60 | ns | 2.5V ≤ VCC ≤ 4.5V | 4 | ||
| HOLD high to output valid | THV | 160 | ns | 1.8V ≤ VCC ≤ 2.5V | 4 | ||
| Internal write cycle time | TWC | 5 | ms | (Note 3) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | gold | TDFN (2x3), 8-lead Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish. | 33 |
CAD (KiCad official)
- Symbol:
25AA640AT-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
25aa640at-i-etched.step/25aa640at-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);25aa640at-i.step/25aa640at-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (36 pp, sha256
a867cd3d278e6f20, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 25AA640AT-I
**Microchip Tech** · Pre-ordered Chips · SOIC-8
25AA640AT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, and a high level deselects it and forces it into Standby mode, though a programming cycle already in progress will complete. |
| 2 | SO | output | Serial Data Output: data is shifted out after the falling edge of SCK during a read, and SO is high-impedance when the device is deselected or paused. |
| 3 | WP | input | Write-Protect: when WPEN is set, a low level on WP disables writes to the nonvolatile bits of the STATUS register, and the WP function is blocked when WPEN is low. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SI | input | Serial Data Input: receives instructions, addresses and data, which are latched on the rising edge of SCK. |
| 6 | SCK | input | Serial Clock input: SI is latched on its rising edge and SO is updated after its falling edge, synchronizing communication with the master. |
| 7 | HOLD | input | Hold input: must be held high when unused; pulling it low while SCK is low pauses serial communication and tri-states SO, and it must be brought high while SCK is low to resume. |
| 8 | VCC | power_in | Supply voltage; the 25AA640A is specified for 1.8V to 5.5V per the Device Selection Table. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| All inputs and outputs w.r.t. VSS | | -0.6 | | 1 | V | Printed as -0.6V to VCC +1.0V; max entry is the +1.0V offset above VCC | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 2 |
| High-level input voltage (min 0.7 VCC; max VCC +1) | VIH1 | 0.7 | | 1 | V (min = 0.7 × VCC; max = VCC + 1 V) | | 2 |
| Low-level input voltage (max 0.3 VCC) | VIL1 | -0.3 | | 0.3 | V (min -0.3 V; max = 0.3 × VCC) | VCC ≥ 2.7V | 2 |
| Low-level input voltage (max 0.2 VCC) | VIL2 | -0.3 | | 0.2 | V (min -0.3 V; max = 0.2 × VCC) | VCC < 2.7V | 2 |
| Low-level output voltage | VOL | | | 0.4 | V | IOL = 2.1 mA | 2 |
| Low-level output voltage (low VCC) | VOL | | | 0.2 | V | IOL = 1.0 mA, VCC < 2.5V | 2 |
| High-level output voltage (min VCC -0.5) | VOH | -0.5 | | | V (min = VCC − 0.5 V) | IOH = -400 µA | 2 |
| Input leakage current | ILI | -1 | | 1 | µA | CS = VCC, VIN = VSS or VCC | 2 |
| Output leakage current | ILO | -1 | | 1 | µA | CS = VCC, VOUT = VSS or VCC | 2 |
| Read operating current | ICC | | | 5 | mA | VCC = 5.5V; FCLK = 10.0 MHz; SO = Open | 2 |
| Read operating current | ICC | | | 2.5 | mA | VCC = 2.5V; FCLK = 5.0 MHz; SO = Open | 2 |
| Write operating current | ICC | | | 5 | mA | VCC = 5.5V | 2 |
| Write operating current | ICC | | | 3 | mA | VCC = 2.5V | 2 |
| Standby current (85°C) | ICCS | | | 1 | µA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C | 2 |
| Clock frequency (4.5V to 5.5V) | FCLK | | | 10 | MHz | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock frequency (2.5V to 4.5V) | FCLK | | | 5 | MHz | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Clock frequency (1.8V to 2.5V) | FCLK | | | 3 | MHz | 1.8V ≤ VCC ≤ 2.5V | 3 |
| CS setup time | TCSS | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS setup time | TCSS | 100 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| CS setup time | TCSS | 150 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| CS hold time | TCSH | 100 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| CS hold time | TCSH | 200 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| CS hold time | TCSH | 250 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| CS disable time | TCSD | 50 | | | ns | | 3 |
| Data setup time | Tsu | 10 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data setup time | Tsu | 20 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Data setup time | Tsu | 30 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| Data hold time | THD | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Data hold time | THD | 40 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Data hold time | THD | 50 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| CLK rise time | TR | | | 100 | ns | (Note 1) | 3 |
| CLK fall time | TF | | | 100 | ns | (Note 1) | 3 |
| Clock high time | THI | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock high time | THI | 100 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Clock high time | THI | 150 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| Clock low time | TLO | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Clock low time | TLO | 100 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Clock low time | TLO | 150 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| Output valid from clock low | TV | | | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| Output valid from clock low | TV | | | 100 | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| Output valid from clock low | TV | | | 160 | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| Output disable time | TDIS | | | 40 | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 3 |
| Output disable time | TDIS | | | 80 | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 3 |
| Output disable time | TDIS | | | 160 | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 3 |
| HOLD setup time | THS | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 3 |
| HOLD setup time | THS | 40 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 3 |
| HOLD setup time | THS | 80 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 3 |
| HOLD hold time | THH | 20 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD hold time | THH | 40 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 4 |
| HOLD hold time | THH | 80 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 4 |
| HOLD low to output High-Z | THZ | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V (Note 1) | 4 |
| HOLD low to output High-Z | THZ | 60 | | | ns | 2.5V ≤ VCC ≤ 4.5V (Note 1) | 4 |
| HOLD low to output High-Z | THZ | 160 | | | ns | 1.8V ≤ VCC ≤ 2.5V (Note 1) | 4 |
| HOLD high to output valid | THV | 30 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| HOLD high to output valid | THV | 60 | | | ns | 2.5V ≤ VCC ≤ 4.5V | 4 |
| HOLD high to output valid | THV | 160 | | | ns | 1.8V ≤ VCC ≤ 2.5V | 4 |
| Internal write cycle time | TWC | | | 5 | ms | (Note 3) | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | gold | TDFN (2x3), 8-lead Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish. | 33 |
## CAD (KiCad official)
- Symbol: `25AA640AT-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `25aa640at-i-etched.step` / `25aa640at-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `25aa640at-i.step` / `25aa640at-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/25aa640at-i-datasheet.pdf) (36 pp, sha256 `a867cd3d278e6f20`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/25aa640at-i-datasheet.pdf)