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25AA1024-I

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Microchip Tech Pre-ordered Chips, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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25AA1024-I

Microchip Tech · Pre-ordered Chips · PDIP-8

25AA1024-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select: a low level selects the device, a high level deselects it and forces Standby mode, and a low level is required on CS after power-up before any sequence is initiated.
2 SO output Serial Data Output: during a read cycle, data is shifted out after the falling edge of SCK, and SO goes to the high-impedance state when the device is deselected or HOLD is pulled low.
3 WP input Write-Protect: when WP is low and the WPEN bit in the STATUS register is high, writes to the nonvolatile STATUS register bits are disabled, and the WP pin function is blocked when WPEN is low.
4 VSS power_in Ground reference for the device.
5 SI input Serial Data Input: receives instructions, addresses and data, which are latched on the rising edge of the serial clock.
6 SCK input Serial Clock: synchronizes communication with the master, with SI latched on the rising edge and SO updated after the falling edge of the clock.
7 HOLD input Hold Input: must be held high when unused, and pulling it low while SCK is low pauses serial communication and tri-states SO, with SI, SCK and SO ignored while paused.
8 VCC power_in Supply Voltage: the device operates from 1.8V to 5.5V over the 0°C to +85°C range, and from 2.0V to 5.5V over the -40°C to +85°C industrial range.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level Input Voltage VIH1 0.7 ×VCC 2
High-level Input Voltage (upper limit) VIH1 1 V from VCC 2
Low-level Input Voltage VIL1 -0.3 V VCC ≥ 2.7V 2
Low-level Input Voltage VIL1 0.3 ×VCC VCC ≥ 2.7V 2
Low-level Input Voltage VIL2 0.2 ×VCC VCC < 2.7V 2
Low-level Output Voltage VOL 0.4 V IOL = 2.1 mA 2
Low-level Output Voltage VOL 0.2 V IOL = 1.0 mA, VCC < 2.5V 2
High-level Output Voltage VOH -0.2 V from VCC IOH = -400 µA 2
Input Leakage Current ILI -1 1 µA CS = VCC, VIN = VSS or VCC 2
Output Leakage Current ILO -1 1 µA CS = VCC, VOUT = VSS or VCC 2
Internal Capacitance (all inputs and outputs) CINT 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) 2
Operating Current ICCREAD 10 mA VCC = 5.5V; FCLK = 20.0 MHz; SO = Open 2
Operating Current ICCREAD 5 mA VCC = 2.5V; FCLK = 10.0 MHz; SO = Open 2
Write Operating Current ICCWRITE 7 mA VCC = 5.5V 2
Write Operating Current ICCWRITE 5 mA VCC = 2.5V 2
Standby Current ICCS 12 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C 2
Deep Power-down Current ICCSPD 1 µA CS = VCC = 2.5V, Inputs tied to VCC or VSS, 85°C 2
All inputs and outputs w.r.t. VSS (lower limit) -0.6 V w.r.t. VSS 2
All inputs and outputs w.r.t. VSS (upper limit) 1 V from VCC w.r.t. VSS 2
Storage Temperature -65 150 °C 2
Ambient Temperature under Bias -40 125 °C 2
ESD Protection on all pins 4 kV on all pins 2
Clock Frequency FCLK 20 MHz 4.5 ≤ VCC ≤ 5.5 3
Clock Frequency FCLK 10 MHz 2.5 ≤ VCC < 4.5 3
Clock Frequency FCLK 2 MHz 2.0 ≤ VCC < 2.5 3
CS Setup Time TCSS 25 ns 4.5 ≤ VCC ≤ 5.5 3
CS Setup Time TCSS 50 ns 2.5 ≤ VCC < 4.5 3
CS Setup Time TCSS 250 ns 2.0 ≤ VCC < 2.5 3
CS Hold Time TCSH 50 ns 4.5 ≤ VCC ≤ 5.5 3
CS Hold Time TCSH 100 ns 2.5 ≤ VCC < 4.5 3
CS Hold Time TCSH 500 ns 2.0 ≤ VCC < 2.5 3
Data Setup Time TSU 5 ns 4.5 ≤ VCC ≤ 5.5 3
Data Setup Time TSU 10 ns 2.5 ≤ VCC < 4.5 3
Data Setup Time TSU 50 ns 2.0 ≤ VCC < 2.5 3
Data Hold Time THD 10 ns 4.5 ≤ VCC ≤ 5.5 3
Data Hold Time THD 20 ns 2.5 ≤ VCC < 4.5 3
Data Hold Time THD 100 ns 2.0 ≤ VCC < 2.5 3
Clock High Time THI 25 ns 4.5 ≤ VCC ≤ 5.5 3
Clock High Time THI 50 ns 2.5 ≤ VCC < 4.5 3
Clock High Time THI 250 ns 2.0 ≤ VCC < 2.5 3
Clock Low Time TLO 25 ns 4.5 ≤ VCC ≤ 5.5 3
Clock Low Time TLO 50 ns 2.5 ≤ VCC < 4.5 3
Clock Low Time TLO 250 ns 2.0 ≤ VCC < 2.5 3
Output Valid from Clock Low TV 25 ns 4.5 ≤ VCC ≤ 5.5 3
Output Valid from Clock Low TV 50 ns 2.5 ≤ VCC < 4.5 3
Output Valid from Clock Low TV 250 ns 2.0 ≤ VCC < 2.5 3
Output Disable Time TDIS 25 ns 4.5 ≤ VCC ≤ 5.5 4
Output Disable Time TDIS 50 ns 2.5 ≤ VCC < 4.5 4
Output Disable Time TDIS 250 ns 2.0 ≤ VCC < 2.5 4
HOLD Setup Time THS 10 ns 4.5 ≤ VCC ≤ 5.5 4
HOLD Setup Time THS 20 ns 2.5 ≤ VCC < 4.5 4
HOLD Setup Time THS 100 ns 2.0 ≤ VCC < 2.5 4
HOLD Hold Time THH 10 ns 4.5 ≤ VCC ≤ 5.5 4
HOLD Hold Time THH 20 ns 2.5 ≤ VCC < 4.5 4
HOLD Hold Time THH 100 ns 2.0 ≤ VCC < 2.5 4
HOLD Low to Output High Z THZ 15 ns 4.5 ≤ VCC ≤ 5.5 4
HOLD Low to Output High Z THZ 30 ns 2.5 ≤ VCC < 4.5 4
HOLD Low to Output High Z THZ 150 ns 2.0 ≤ VCC < 2.5 4
HOLD High to Output Valid THV 15 ns 4.5 ≤ VCC ≤ 5.5 4
HOLD High to Output Valid THV 30 ns 2.5 ≤ VCC < 4.5 4
HOLD High to Output Valid THV 150 ns 2.0 ≤ VCC < 2.5 4
Internal Write Cycle Time TWC 6 ms Byte or Page mode and Page Erase 4

CAD (KiCad official)

  • Symbol: 25AA1024-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: 25aa1024-i-etched.step / 25aa1024-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25aa1024-i.step / 25aa1024-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 21f8fc827265aaf6, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF