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25AA040A-I

Microchip Tech · EEPROM · PDIP-8

25AA040A-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and a low-to-high transition after a valid write sequence starts the internal write cycle.
2 SO tri_state Serial Data Output: data is shifted out after the falling edge of SCK during a read, and the pin goes high-impedance when the device is deselected or HOLD is low.
3 WP input Write-Protect input: when low, all writes to the array or STATUS register are disabled; when high, all functions including nonvolatile writes operate normally.
4 VSS power_in Ground.
5 SI input Serial Data Input: receives instructions, addresses and data, latched on the rising edge of SCK.
6 SCK input Serial Clock input: synchronizes communication, with inputs latched on the rising edge and SO updated after the falling edge.
7 HOLD input Hold input: pulling it low pauses serial communication without resetting the sequence, and it must be held high when the function is not used.
8 VCC power_in Supply voltage: 1.8V to 5.5V for the 25AA040A, with an absolute maximum of 6.5V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (Industrial) VCC 1.8 5.5 V Industrial (I) 2
Operating Temperature (Industrial) TA -40 85 °C Industrial (I) 2
Storage Temperature -65 150 °C 2
Ambient Temperature Under Bias -40 125 °C 2
ESD Protection on All Pins 4 kV 2
Low-Level Input Voltage 1 VIL1 -0.3 V max 0.3 VCC; VCC ≥ 2.7V (Note 1) 2
Low-Level Input Voltage 2 VIL2 -0.3 V max 0.2 VCC; VCC < 2.7V (Note 1) 2
Low-Level Output Voltage VOL 0.4 V IOL = 2.1 mA 2
Low-Level Output Voltage VOL 0.2 V IOL = 1.0 mA, VCC = 2.5V 2
Input Leakage Current ILI -1 1 µA CS = VCC, VIN = VSS or VCC 2
Output Leakage Current ILO -1 1 µA CS = VCC, VOUT = VSS or VCC 2
Internal Capacitance (all inputs and outputs) CINT 7 pF TA = +25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) 2
Read Operating Current ICC Read 5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open 2
Read Operating Current ICC Read 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open 2
Write Operating Current ICC Write 5 mA VCC = 5.5V 2
Write Operating Current ICC Write 3 mA VCC = 2.5V 2
Standby Current ICCS 5 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, TA = +125°C 2
Standby Current ICCS 1 µA CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C 2
Clock Frequency FCLK 10 MHz 4.5V ≤ VCC ≤ 5.5V 3
Clock Frequency FCLK 5 MHz 2.5V ≤ VCC < 4.5V 3
Clock Frequency FCLK 3 MHz 1.8V ≤ VCC < 2.5V 3
CS Setup Time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Setup Time TCSS 100 ns 2.5V ≤ VCC < 4.5V 3
CS Setup Time TCSS 150 ns 1.8V ≤ VCC < 2.5V 3
CS Hold Time TCSH 100 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Hold Time TCSH 200 ns 2.5V ≤ VCC < 4.5V 3
CS Hold Time TCSH 250 ns 1.8V ≤ VCC < 2.5V 3
CS Disable Time TCSD 50 ns 3
Data Setup Time Tsu 10 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Setup Time Tsu 20 ns 2.5V ≤ VCC < 4.5V 3
Data Setup Time Tsu 30 ns 1.8V ≤ VCC < 2.5V 3
Data Hold Time THD 20 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Hold Time THD 40 ns 2.5V ≤ VCC < 4.5V 3
Data Hold Time THD 50 ns 1.8V ≤ VCC < 2.5V 3
CLK Rise Time TR 100 ns Note 1 3
CLK Fall Time TF 100 ns Note 1 3
Clock High Time THI 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock High Time THI 100 ns 2.5V ≤ VCC < 4.5V 3
Clock High Time THI 150 ns 1.8V ≤ VCC < 2.5V 3
Clock Low Time TLO 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock Low Time TLO 100 ns 2.5V ≤ VCC < 4.5V 3
Clock Low Time TLO 150 ns 1.8V ≤ VCC < 2.5V 3
Clock Delay Time TCLD 50 ns 3
Clock Enable Time TCLE 50 ns 3
Output Valid from Clock Low TV 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Output Valid from Clock Low TV 100 ns 2.5V ≤ VCC < 4.5V 3
Output Valid from Clock Low TV 160 ns 1.8V ≤ VCC < 2.5V 3
Output Hold Time THO 0 ns Note 1 3
Output Disable Time TDIS 40 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 3
Output Disable Time TDIS 80 ns 2.5V ≤ VCC < 4.5V (Note 1) 3
Output Disable Time TDIS 160 ns 1.8V ≤ VCC < 2.5V (Note 1) 3
HOLD Setup Time THS 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD Setup Time THS 40 ns 2.5V ≤ VCC < 4.5V 4
HOLD Setup Time THS 80 ns 1.8V ≤ VCC < 2.5V 4
HOLD Hold Time THH 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD Hold Time THH 40 ns 2.5V ≤ VCC < 4.5V 4
HOLD Hold Time THH 80 ns 1.8V ≤ VCC < 2.5V 4
HOLD Low to Output High-Z THZ 30 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
HOLD Low to Output High-Z THZ 60 ns 2.5V ≤ VCC < 4.5V (Note 1) 4
HOLD Low to Output High-Z THZ 160 ns 1.8V ≤ VCC < 2.5V (Note 1) 4
HOLD High to Output Valid THV 30 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD High to Output Valid THV 60 ns 2.5V ≤ VCC < 4.5V 4
HOLD High to Output Valid THV 160 ns 1.8V ≤ VCC < 2.5V 4
Internal Write Cycle Time (byte or page) TWC 5 ms Note 2 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 25

CAD (KiCad official)

  • Symbol: 25AA040A-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: 25aa040a-i-etched.step / 25aa040a-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25aa040a-i.step / 25aa040a-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (42 pp, sha256 e11efc462b198265, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF