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25AA02E48T-I

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Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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25AA02E48T-I

Microchip Tech · EEPROM · SOIC-8

25AA02E48T-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select input: a low level selects the device, while a high level deselects it and forces Standby mode, and a low level is required after power-up before any sequence is initiated.
2 SO tri_state Serial Data Output: data is shifted out after the falling edge of SCK during a read, and the pin goes to high-impedance when the device is deselected or HOLD is low.
3 WP input Hardware write-protect input: when low, all writes to the array or STATUS register are disabled while other operations function normally, and the write enable latch is reset.
4 VSS power_in Ground reference for the device.
5 SI input Serial Data Input: receives instructions, addresses and data, latched on the rising edge of SCK.
6 SCK input Serial Clock input that synchronizes communication: SI is latched on its rising edge and SO is updated after its falling edge.
7 HOLD input Hold input used to pause serial communication while selected: it must be brought low while SCK is low, must be held high when unused, and tri-states SO when pulled low.
8 VCC power_in Supply voltage, specified for operation from 1.8V to 5.5V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
All inputs and outputs w.r.t. VSS -0.6 1 V 2
Storage temperature -65 150 °C 2
Ambient temperature under bias -40 85 °C 2
High-Level Input Voltage VIH1 0.7 1 V 2
Low-Level Input Voltage VIL1 -0.3 0.3 V VCC ≥ 2.7V (Note 1) 2
Low-Level Input Voltage VIL2 -0.3 0.2 V VCC < 2.7V (Note 1) 2
Low-Level Output Voltage VOL 0.4 V IOL = 2.1 mA 2
Low-Level Output Voltage VOL 0.2 V IOL = 1.0 mA, VCC < 2.5V 2
High-Level Output Voltage VOH -0.5 V IOH = -400 µA 2
Input Leakage Current ILI -1 1 µA CS = VCC, VIN = VSS or VCC 2
Output Leakage Current ILO -1 1 µA CS = VCC, VOUT = VSS or VCC 2
Internal Capacitance (all inputs and outputs) CINT 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) 2
Operating Current (read) ICCREAD 5 mA VCC = 5.5V; FCLK = 10.0 MHz, SO = Open 2
Operating Current (read) ICCREAD 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz, SO = Open 2
Operating Current (write) ICCWRITE 5 mA VCC = 5.5V 2
Operating Current (write) ICCWRITE 3 mA VCC = 2.5V 2
Standby Current ICCS 1 µA CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C 2
Clock Frequency FCLK 10 MHz 4.5V ≤ VCC ≤ 5.5V 3
Clock Frequency FCLK 5 MHz 2.5V ≤ VCC ≤ 4.5V 3
Clock Frequency FCLK 3 MHz 1.8V ≤ VCC ≤ 2.5V 3
CS Setup Time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Setup Time TCSS 100 ns 2.5V ≤ VCC ≤ 4.5V 3
CS Setup Time TCSS 150 ns 1.8V ≤ VCC ≤ 2.5V 3
CS Hold Time TCSH 100 ns 4.5V ≤ VCC ≤ 5.5V 3
CS Hold Time TCSH 200 ns 2.5V ≤ VCC ≤ 4.5V 3
CS Hold Time TCSH 250 ns 1.8V ≤ VCC ≤ 2.5V 3
CS Disable Time TCSD 50 ns 3
Data Setup Time TSU 10 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Setup Time TSU 20 ns 2.5V ≤ VCC ≤ 4.5V 3
Data Setup Time TSU 30 ns 1.8V ≤ VCC ≤ 2.5V 3
Data Hold Time THD 20 ns 4.5V ≤ VCC ≤ 5.5V 3
Data Hold Time THD 40 ns 2.5V ≤ VCC ≤ 4.5V 3
Data Hold Time THD 50 ns 1.8V ≤ VCC ≤ 2.5V 3
Clock High Time THI 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock High Time THI 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock High Time THI 150 ns 1.8V ≤ VCC ≤ 2.5V 3
Clock Low Time TLO 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock Low Time TLO 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Clock Low Time TLO 150 ns 1.8V ≤ VCC ≤ 2.5V 3
Output Valid from Clock Low TV 50 ns 4.5V ≤ VCC ≤ 5.5V 3
Output Valid from Clock Low TV 100 ns 2.5V ≤ VCC ≤ 4.5V 3
Output Valid from Clock Low TV 160 ns 1.8V ≤ VCC ≤ 2.5V 3
Output Disable Time TDIS 40 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
Output Disable Time TDIS 80 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 4
Output Disable Time TDIS 160 ns 1.8V ≤ VCC ≤ 2.5V (Note 1) 4
HOLD Setup Time THS 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD Setup Time THS 40 ns 2.5V ≤ VCC ≤ 4.5V 4
HOLD Setup Time THS 80 ns 1.8V ≤ VCC ≤ 2.5V 4
HOLD Hold Time THH 20 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD Hold Time THH 40 ns 2.5V ≤ VCC ≤ 4.5V 4
HOLD Hold Time THH 80 ns 1.8V ≤ VCC ≤ 2.5V 4
HOLD Low to Output High-Z THZ 30 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
HOLD Low to Output High-Z THZ 60 ns 2.5V ≤ VCC ≤ 4.5V (Note 1) 4
HOLD Low to Output High-Z THZ 160 ns 1.8V ≤ VCC ≤ 2.5V (Note 1) 4
HOLD High to Output Valid THV 30 ns 4.5V ≤ VCC ≤ 5.5V 4
HOLD High to Output Valid THV 60 ns 2.5V ≤ VCC ≤ 4.5V 4
HOLD High to Output Valid THV 160 ns 1.8V ≤ VCC ≤ 2.5V 4
Internal Write Cycle Time (byte or page) TWC 5 ms Note 2 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 18

CAD (KiCad official)

  • Symbol: 25AA02E48T-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 25aa02e48t-i-etched.step / 25aa02e48t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 25aa02e48t-i.step / 25aa02e48t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (30 pp, sha256 50c429b3f1b0b8cc, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF