# 24LC515-I

**Microchip Tech** · Pre-ordered MCUs · PDIP-8

24LC515-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | User-configurable chip address input that must be driven to logic 0 or 1 before normal operation and is compared with the slave address bits for multi-device selection. |
| 2 | A1 | input | User-configurable chip address input that must be driven to logic 0 or 1 before normal operation and is compared with the slave address bits for multi-device selection. |
| 3 | A2 | input | Non-configurable chip select input that must be tied to VCC, as the device will not operate if it is floating or held at VSS. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Open-drain serial data line requiring a pull-up to VCC (typically 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz), with data allowed to change only while SCL is low except for Start and Stop conditions. |
| 6 | SCL | input | Serial clock input used to synchronize data transfer to and from the device. |
| 7 | WP | input | Write-protect input that must be tied to VSS to enable write operations or to VCC to inhibit writes while reads are unaffected. |
| 8 | VCC | power_in | Supply voltage of +2.5 to 5.5V for the 24LC515 (+1.7 to 5.5V applies to the 24AA515). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC | VCC | 2.5 |  | 5.5 | V | 24LC515 VCC range | 1 |
| Industrial ambient temperature | TA | -40 |  | 85 | °C | Industrial (I) temperature range | 1 |
| Voltage on all inputs and outputs |  | -0.6 |  |  | V | w.r.t. VSS; upper limit VCC +1.0V | 2 |
| Ambient temperature with power applied |  | -40 |  | 125 | °C | Power applied | 2 |
| Storage temperature |  | -65 |  | 150 | °C |  | 2 |
| ESD protection on all pins |  | 4 |  |  | kV |  | 2 |
| High-level input voltage | VIH | 0.7 |  |  | x VCC | A0, A1, SCL, SDA and WP pins; VCC = 1.7V to 5.5V | 2 |
| Low-level input voltage | VIL |  |  | 0.3 | x VCC | A0, A1, SCL, SDA and WP pins; VCC ≥ 2.5V | 2 |
| Hysteresis of Schmitt Trigger inputs | VHYS | 0.05 |  |  | x VCC | SDA, SCL pins; VCC ≥ 2.5V (Note) | 2 |
| Low-level output voltage | VOL |  |  | 0.4 | V | IOL = 3.0 mA @ VCC = 4.5V | 2 |
| Input leakage current | ILI | -1 |  | 1 | μA | VIN = VSS or VCC, WP = VSS | 2 |
| Output leakage current | ILO | -1 |  | 1 | μA | VOUT = VSS or VCC | 2 |
| Pin capacitance (all inputs/outputs) | CIN, COUT |  |  | 10 | pF | VCC = 5.0V (Note); TA = 25°C, FCLK = 1 MHz | 2 |
| Read operating current | ICC |  |  | 500 | μA | VCC = 5.5V, SCL = 400 kHz | 2 |
| Write operating current | ICC |  |  | 3 | mA | VCC = 5.5V | 2 |
| Standby current | Iccs |  |  | 5 | μA | SCL = SDA = VCC = 5.5V; A0, A1, WP = VSS, A2 = VCC | 2 |
| Clock frequency | FCLK |  |  | 400 | kHz | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Clock high time | THIGH | 600 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Clock low time | TLOW | 1300 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| SDA and SCL rise time | TR |  |  | 300 | ns | 2.5V ≤ VCC ≤ 5.5V (Note 1) | 3 |
| SDA and SCL fall time | TF |  |  | 300 | ns | All except 24FC515 (Note 1) | 3 |
| Start condition hold time | THD:STA | 600 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Start condition setup time | TSU:STA | 600 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Data input hold time | THD:DAT | 0 |  |  | ns | Note 2 | 3 |
| Data input setup time | TSU:DAT | 100 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Stop condition setup time | TSU:STO | 600 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| WP setup time | TSU:WP | 600 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| WP hold time | THD:WP | 1300 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Output valid from clock | TAA |  |  | 900 | ns | 2.5V ≤ VCC ≤ 5.5V (Note 2) | 3 |
| Bus free time | TBUF | 1300 |  |  | ns | 2.5V ≤ VCC ≤ 5.5V | 3 |
| Output fall time from VIH minimum to VIL maximum | TOF |  |  | 250 | ns | CB ≤ 100 pF; All except 24FC515 (Note 1) | 3 |
| Input filter spike suppression (SDA and SCL pins) | TSP |  |  | 50 | ns | All except 24FC515 (Notes 1 and 3) | 3 |
| Write cycle time (byte or page) | TWC |  |  | 5 | ms |  | 3 |
| Endurance |  | 1 |  |  | M cycles | 25°C (Note 4) | 3 |

## CAD (KiCad official)

- Symbol: `24LC515-I`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `24lc515-i-etched.step` / `24lc515-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `24lc515-i.step` / `24lc515-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/24lc515-i-datasheet.pdf) (24 pp, sha256 `c14797231668da84`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/24lc515-i-datasheet.pdf)