# 24LC256

**Microchip Technology** · I2C serial EEPROM · SOIC-8

256 Kbit (32K x 8) I2C serial EEPROM in a SOIC-8 package. It runs from 2.5-5.5 V at up to 400 kHz, with a 64-byte page-write buffer and a hardware write-protect pin. Three address pins (A0-A2) let up to eight devices share one I2C bus. The default off-chip non-volatile storage for configuration, logs, and calibration next to an MCU.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | User-configurable chip-select address bit 0. Compared with the corresponding bit of the incoming slave address; must be tied to VCC or VSS. Combined with A1/A2 to allow up to 8 devices on one I2C bus. |
| 2 | A1 | input | User-configurable chip-select address bit 1. Compared with the corresponding bit of the incoming slave address; must be tied to VCC or VSS. |
| 3 | A2 | input | User-configurable chip-select address bit 2. Compared with the corresponding bit of the incoming slave address; must be tied to VCC or VSS. |
| 4 | VSS | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Bidirectional serial address/data I/O. Open-drain output; requires an external pull-up resistor to VCC (typ. 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz). Data may change only while SCL is low. |
| 6 | SCL | input | Serial clock input used to synchronize data transfers to and from the device. Schmitt-trigger input for noise suppression. |
| 7 | WP | input | Write-protect input. Tie to VSS to enable writes; tie to VCC to inhibit write operations (reads are unaffected). Must not be left floating. |
| 8 | VCC | power_in | Positive supply input. Operating range 2.5V to 5.5V for 24LC256. Decouple with a local bypass capacitor to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Type | I2C serial EEPROM |
| Capacity | 256 Kbit (32K x 8) |
| Interface | I2C, up to 400 kHz |
| Supply voltage | 2.5-5.5 V |
| Page write | 64-byte buffer |
| Write protect | WP pin (hardware) |
| Addressing | A0-A2 (up to 8 on a bus) |
| Package | SOIC-8 |
| Body (L×W×H) | 4.9 × 3.9 × 1.75 mm |

## Ordering variants

- `24LC256-I/SN (SOIC-8, tube)`
- `24LC256T-I/SN (SOIC-8, tape & reel)`

## CAD (KiCad official)

- Symbol: `Memory_EEPROM:24LC256`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D)
- 3D model files: `24lc256-etched.step` / `24lc256-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `24lc256.step` / `24lc256.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Technology datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/24AA256-24LC256-24FC256-Data-Sheet-20001203W.pdf) (42 pp, sha256 `ee9e9f15a6ce94e3`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude) — every pin and dimension is cited to a datasheet page; refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/24lc256-datasheet.pdf)