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24LC22A-I

Microchip Tech · EEPROM · SOIC-8

24LC22A-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 NC unconnected No internal connection.
3 NC unconnected No internal connection.
4 VSS power_in Ground.
5 SDA bidirectional Open-drain serial address/data I/O that needs a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz), and also carries data in Transmit-Only mode.
6 SCL input Serial clock input for Bidirectional mode that also signals the switch from Transmit-Only to Bidirectional mode, and must remain high for the chip to continue operation in Transmit-Only mode.
7 VCLK input Serial clock input for Transmit-Only mode (DDC1) where each bit is clocked out on the rising edge, and a high level is required in Bidirectional mode to enable write capability.
8 VCC power_in +2.5V to 5.5V power supply.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage absolute maximum VCC 7 V 2
Input/output voltage w.r.t. VSS -0.6 1 V -0.6V to VCC +1.0V (max is VCC + 1.0V) 2
Storage temperature -65 150 °C 2
Ambient temp with power applied -40 125 °C 2
Soldering temperature of leads 240 °C 10 seconds 2
ESD protection on all pins 4 kV 2
Supply voltage operating VCC 2.5 5.5 V Industrial 2
Operating ambient temperature TAMB -40 85 °C Industrial (I) 2
High-level input voltage SCL/SDA VIH 0.7 V x VCC; SCL and SDA pins 2
Low-level input voltage SCL/SDA VIL 0.3 V x VCC; SCL and SDA pins 2
High-level input voltage VCLK VIH 2 V VCC ≥ 2.7V (Note) 2
Low-level input voltage VCLK VIL 0.2 V x VCC; VCC ≤ 2.7V (Note) 2
Hysteresis of Schmitt trigger inputs VHYS 0.05 V x VCC (Note) 2
Low-level output voltage VOL1 0.4 V IOL = 3 mA, VCC = 2.5V (Note) 2
Low-level output voltage VOL2 0.6 V IOL = 6 mA, VCC = 2.5V 2
Input leakage current ILI -10 10 µA VIN = VSS or VCC 2
Output leakage current ILO -10 10 µA VOUT = VSS or VCC 2
Pin capacitance (all inputs/outputs) CIN, COUT 10 pF VCC = 5.0V (Note), TAMB = 25°C, FCLK = 1 MHz 2
Write operating current ICC WRITE 3 mA VCC = 5.5V 2
Read operating current ICC READ 1 mA VCC = 5.5V, SCL = 400 kHz 2
Standby current ICCS 30 µA VCC = 3.0V, SDA = SCL = VCC, VCLK = VSS 2
Standby current ICCS 100 µA VCC = 5.5V, SDA = SCL = VCC, VCLK = VSS 2
Clock frequency FCLK 100 kHz 2.5V ≤ VCC ≤ 5.5V 3
Clock frequency FCLK 400 kHz 4.5V ≤ VCC ≤ 5.5V 3
Clock high time THIGH 4000 ns 2.5V ≤ VCC ≤ 5.5V 3
Clock high time THIGH 600 ns 4.5V ≤ VCC ≤ 5.5V 3
Clock low time TLOW 4700 ns 2.5V ≤ VCC ≤ 5.5V 3
Clock low time TLOW 1300 ns 4.5V ≤ VCC ≤ 5.5V 3
SDA and SCL rise time TR 1000 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) 3
SDA and SCL rise time TR 300 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 3
SDA and SCL fall time TF 300 ns (Note 1) 3
Start condition hold time THD:STA 4000 ns 2.5V ≤ VCC ≤ 5.5V 3
Start condition hold time THD:STA 600 ns 4.5V ≤ VCC ≤ 5.5V 3
Start condition setup time TSU:STA 4700 ns 2.5V ≤ VCC ≤ 5.5V 3
Start condition setup time TSU:STA 600 ns 4.5V ≤ VCC ≤ 5.5V 3
Data input hold time THD:DAT 0 ns (Note 2) 3
Data input setup time TSU:DAT 250 ns 2.5V ≤ VCC ≤ 5.5V 3
Data input setup time TSU:DAT 100 ns 4.5V ≤ VCC ≤ 5.5V 3
Stop condition setup time TSU:STO 4000 ns 2.5V ≤ VCC ≤ 5.5V 3
Stop condition setup time TSU:STO 600 ns 4.5V ≤ VCC ≤ 5.5V 3
Output valid from clock TAA 3500 ns 2.5V ≤ VCC ≤ 5.5V (Note 2) 3
Output valid from clock TAA 900 ns 4.5V ≤ VCC ≤ 5.5V (Note 2) 3
Bus free time TBUF 4700 ns 2.5V ≤ VCC ≤ 5.5V 3
Bus free time TBUF 1300 ns 4.5V ≤ VCC ≤ 5.5V 3
Output fall time from VIH min to VIL max TOF 20 250 ns 2.5V ≤ VCC ≤ 5.5V (Note 1); min printed 20+0.1CB 3
Output fall time from VIH min to VIL max TOF 250 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 3
Input filter spike suppression (SDA, SCL) TSP 50 ns (Notes 1 and 3) 3
Write cycle time (byte or page) TWR 10 ms 3
Output valid from VCLK TVAA 2000 ns 2.5V ≤ VCC ≤ 5.5V column (first value) 3
Output valid from VCLK TVAA 1000 ns 4.5V ≤ VCC ≤ 5.5V column (second value) 3
VCLK high time TVHIGH 4000 ns first value (2.5V-5.5V) 3
VCLK high time TVHIGH 600 ns second value (4.5V-5.5V) 3
VCLK low time TVLOW 4700 ns first value (2.5V-5.5V) 3
VCLK low time TVLOW 1300 ns second value (4.5V-5.5V) 3
VCLK setup time TVHST 0 ns 3
VCLK hold time TSPVL 4000 ns first value (2.5V-5.5V) 3
VCLK hold time TSPVL 600 ns second value (4.5V-5.5V) 3
Mode transition time TVHZ 1000 ns first value (2.5V-5.5V) 3
Mode transition time TVHZ 500 ns second value (4.5V-5.5V) 3
Transmit-Only power up time TVPU 0 ns 3
Input filter spike suppression (VCLK pin) TSPV 100 ns 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Package: P = Plastic DIP (300 mil Body), 8-Lead SN = Plastic SOIC (3.90 mm Body), 8-Lead 21

CAD (KiCad official)

  • Symbol: 24LC22A-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 24lc22a-i-etched.step / 24lc22a-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 24lc22a-i.step / 24lc22a-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (24 pp, sha256 a50dff19a7eca8ad, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF