← Commit history

Initial commit: component/24c64bn

Ray ·ae6f7a6ba1 ·
2 files changed +87
README.mdadded+53
@@ -0,0 +1,53 @@+# 24C64BN++**XBLW 24C64BN XBLW** · EEPROM · SOP-8++24C64BN from XBLW 24C64BN XBLW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A0 | input | Device address input bit 0. Hard-wire to VIH or VIL to set the least-significant chip-select address bit; matched against the 5th address bit sent on the I2C bus. Internally pulled to VIL if left unconnected. |+| 2 | A1 | input | Device address input bit 1. Hard-wire to VIH or VIL to set the middle chip-select address bit; matched against the 6th address bit sent on the I2C bus. Internally recognized as VIL if left floating. |+| 3 | A2 | input | Device address input bit 2. Hard-wire to VIH or VIL to set the most-significant chip-select address bit; matched against the 7th address bit sent on the I2C bus. Internally recognized as VIL if left floating. |+| 4 | GND | power_in | Device ground reference (0 V). Common return for VCC and all logic signals. |+| 5 | SDA | bidirectional | I2C serial data line. Bi-directional, open-drain output - requires an external pull-up resistor to VCC and can be wire-OR'ed with other open-drain devices on the bus. |+| 6 | SCL | input | I2C serial clock input. Data on SDA is latched into the EEPROM on the rising edge; data is clocked out on the falling edge. Rated 400 kHz at 1.8 V and up to 1 MHz at 2.5-5.5 V. |+| 7 | WP | input | Hardware write-protect input. Tie to VIL (or leave unconnected) to allow programming of the EEPROM array; tie to VIH / VCC to disable all program/erase operations. Read operations are unaffected by WP state. |+| 8 | VCC | power_in | Positive supply input. Operating range 1.8 V to 5.5 V; absolute maximum 8 V. Bypass to GND with a local 100 nF ceramic capacitor. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XBLW 24C64BN XBLW |+| Package | SOP-8 |+| Category | Memory |+| Pins | 8 |++## Ordering variants++- `24C64BNBN`+- `24C64BNN`+- `24C64BNMN`+- `24C64BNTN`+- `24C64BNDN`+- `24C64BND6`+- `24C64BNS`++## CAD (KiCad official)++- Symbol: `24C64BN`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XBLW 24C64BN XBLW datasheet](docs/24c64bn-datasheet.pdf) (18 pp, sha256 `c0329401d1e9b2e0`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/24c64bn-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "24c64bn",+  "version": "0.1.0",+  "type": "component",+  "description": "XBLW 24C64BN XBLW EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "memory",+    "24c64bn"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "24c64bn.kicad_sym",+    "24c64bn.kicad_mod",+    "24c64bn.glb",+    "24c64bn.step",+    "24c64bn.lbr",+    "docs/hero.png",+    "docs/24c64bn-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file