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24c64bn: factory component page (tier=lcsc)

Ray ·9e00bb0adb · ·parent 04bd1d9
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "24c64bn",+  "title": "24C64BN",+  "brief": "XBLW 24C64BN XBLW EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "XBLW 24C64BN XBLW EEPROM, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "24c64bn"   ],+  "component": {+    "mpn": "24C64BN",+    "manufacturer": "XBLW 24C64BN XBLW",+    "package": "SOP-8",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "EEPROM",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191805_XBLW-24C64BN-XBLW_C18723547.pdf",+    "parts": {+      "symbol": "24c64bn.kicad_sym",+      "footprint": "24c64bn.kicad_mod",+      "model_3d": "24c64bn.glb",+      "model_3d_step": "24c64bn.step",+      "lbr": "24c64bn.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A0",+        "type": "input",+        "description": "Device address input bit 0. Hard-wire to VIH or VIL to set the least-significant chip-select address bit; matched against the 5th address bit sent on the I2C bus. Internally pulled to VIL if left unconnected."+      },+      {+        "number": "2",+        "name": "A1",+        "type": "input",+        "description": "Device address input bit 1. Hard-wire to VIH or VIL to set the middle chip-select address bit; matched against the 6th address bit sent on the I2C bus. Internally recognized as VIL if left floating."+      },+      {+        "number": "3",+        "name": "A2",+        "type": "input",+        "description": "Device address input bit 2. Hard-wire to VIH or VIL to set the most-significant chip-select address bit; matched against the 7th address bit sent on the I2C bus. Internally recognized as VIL if left floating."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground reference (0 V). Common return for VCC and all logic signals."+      },+      {+        "number": "5",+        "name": "SDA",+        "type": "bidirectional",+        "description": "I2C serial data line. Bi-directional, open-drain output - requires an external pull-up resistor to VCC and can be wire-OR'ed with other open-drain devices on the bus."+      },+      {+        "number": "6",+        "name": "SCL",+        "type": "input",+        "description": "I2C serial clock input. Data on SDA is latched into the EEPROM on the rising edge; data is clocked out on the falling edge. Rated 400 kHz at 1.8 V and up to 1 MHz at 2.5-5.5 V."+      },+      {+        "number": "7",+        "name": "WP",+        "type": "input",+        "description": "Hardware write-protect input. Tie to VIL (or leave unconnected) to allow programming of the EEPROM array; tie to VIH / VCC to disable all program/erase operations. Read operations are unaffected by WP state."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply input. Operating range 1.8 V to 5.5 V; absolute maximum 8 V. Bypass to GND with a local 100 nF ceramic capacitor."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2310191805_XBLW-24C64BN-XBLW_C18723547.pdf",+        "pages": 18,+        "sha256": "c0329401d1e9b2e0",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "XBLW 24C64BN XBLW",+      "Package": "SOP-8",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "24c64bn"+  ],+  "discovery_pitch": "24C64BN (XBLW 24C64BN XBLW) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/24c64bn-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file