component
24C32N
Public Made by Adomby adom
XBLW EEPROM, DIP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.2.2
1f44fa4
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{
"schema_version": 1,
"type": "component",
"slug": "24c32n",
"title": "24C32N",
"brief": "XBLW EEPROM, DIP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.2",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"memory",
"24c32n"
],
"component": {
"mpn": "24C32N",
"manufacturer": "XBLW",
"package": "DIP-8",
"pin_count": 8,
"category": "Memory",
"subcategory": "EEPROM",
"datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403141555_XBLW-24C32N-XBLW_C18723552.pdf",
"parts": {
"symbol": "24c32n.kicad_sym",
"footprint": "24c32n.kicad_mod",
"model_3d": "24c32n-hero.glb",
"model_3d_plain": "24c32n.glb",
"model_3d_step": "24c32n-etched.step",
"model_3d_step_plain": "24c32n.step",
"lbr": "24c32n.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "A0",
"type": "input",
"description": "Device/chip select address input bit 0. Hardwire to VCC (VIH) or GND (VIL) to set the low bit of the 3-bit slave address; recommend a 10kΩ or smaller pull to a known state to avoid capacitive-coupling ambiguity. Internally recognized as VIL if left unconnected."
},
{
"number": "2",
"name": "A1",
"type": "input",
"description": "Device/chip select address input bit 1. Tie to VCC or GND to set the middle bit of the slave-address field; recommend ≤10kΩ pull. Internally recognized as VIL if left floating."
},
{
"number": "3",
"name": "A2",
"type": "input",
"description": "Device/chip select address input bit 2 (MSB of the 3-bit hardware address). Tie to VCC or GND; recommend ≤10kΩ pull. Internally recognized as VIL if left floating."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Device ground return (0 V reference)."
},
{
"number": "5",
"name": "SDA",
"type": "bidirectional",
"description": "Serial data line for the 2-wire (I²C-compatible) bus. Open-drain output; requires an external pull-up resistor to VCC and may be wire-ORed with other open-drain devices."
},
{
"number": "6",
"name": "SCL",
"type": "input",
"description": "Serial clock input for the 2-wire bus. Rising edge latches data into the EEPROM; falling edge clocks data out. Schmitt-trigger filtered input; supports 1000 kHz at 2.5-5V and 400 kHz at 1.8V."
},
{
"number": "7",
"name": "WP",
"type": "input",
"description": "Hardware write-protect input. When tied to VIH/VCC, all programming (write) operations to the EEPROM array are disabled; when tied low (VIL) or left floating, writes are enabled. Read operations are unaffected. Recommend a ≤10kΩ pull to a known state."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Main supply input, 1.8V to 5.5V. Decouple locally with a ceramic bypass capacitor (typ. 100 nF) to GND."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403141555_XBLW-24C32N-XBLW_C18723552.pdf",
"pages": 18,
"sha256": "e4967cc78153e97f",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
0,
0
],
"corner": "bottom-right",
"source": "fab-chamfer",
"derived_from": "DIP-8_W7.62mm@sha256:222fb44370968119",
"mark": "synthesised"
},
"models_3d": [
{
"file": "24c32n.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
"extents_mm": [
7.874,
9.27,
6.98
],
"zmin_mm": -3.3,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "4a377a56a8d9e9c0b86c095ef9ecc1869ac19e7f5069a3247b294250bf4f235d",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "24c32n-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
"extents_mm": [
7.874,
9.27,
6.98
],
"zmin_mm": -3.3,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "016f3d962888869fb2f25ea8b8865b6039dc407d9f0b8fe29a48733b978d9c71",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "XBLW",
"Package": "DIP-8",
"Category": "Memory",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"24c32n"
],
"discovery_pitch": "24C32N (XBLW) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"24c32n.kicad_sym",
"24c32n.kicad_mod",
"24c32n.glb",
"24c32n.step",
"24c32n-etched.step",
"24c32n.lbr",
"docs/hero.png",
"docs/24c32n-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"pads.json",
"24c32n-etched.glb",
"24c32n-hero.glb",
"24c32n-hero.overlay.json"
],
"visibility": "public",
"updated_at": "2026-09-24T14:32:12.403Z",
"description": "XBLW EEPROM, DIP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
"org": "adom"
}