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24AA32AFT-I

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Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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24AA32AFT-I

Microchip Tech · EEPROM · SOIC-8

24AA32AFT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Chip address input that must be hard-wired to VCC or VSS (or driven to a logic level before operation) to select the device on a multi-device bus.
2 A1 input Chip address input that must be connected to either VCC or VSS, with its level compared against the corresponding bit of the slave address.
3 A2 input Chip address input that must be connected to either VCC or VSS, allowing up to eight devices on the same bus.
4 VSS power_in Ground reference for the device.
5 SDA bidirectional Open-drain serial address/data I/O requiring a pull-up resistor to VCC (typically 10 kΩ for 100 kHz or 2 kΩ for 400 kHz), with data allowed to change only while SCL is low.
6 SCL input Serial clock input used to synchronize data transfer to and from the device.
7 WP input Write-protect input that must be tied to VSS (writes enabled) or VCC (upper 1/4 of the array, C00h-FFFh, write-inhibited while reads are unaffected).
8 VCC power_in Power supply, specified as +1.7V to 5.5V in the pin table (24LC32AF is specified from 2.5V).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature -65 150 °C 2
Ambient temperature with power applied -40 125 °C 2
ESD protection on all pins 4 kV ESD protection on all pins 2
All inputs and outputs w.r.t. VSS (lower limit) -0.3 V w.r.t. VSS; upper limit printed as VCC +1.0V 2
High-level input voltage VIH 0.7 ×VCC 2
Low-level input voltage VIL 0.3 ×VCC VCC ≥ 2.5V 2
Low-level input voltage VIL 0.2 ×VCC VCC < 2.5V 2
Hysteresis of Schmitt trigger inputs (SDA, SCL) VHYS 0.05 ×VCC VCC ≥ 2.5V (Note 1) 2
Low-level output voltage VOL 0.4 V IOL = 3.0 mA, VCC = 4.5V 2
Input leakage current ILI -1 1 μA VIN = VSS or VCC 2
Output leakage current ILO -1 1 μA VOUT = VSS or VCC 2
Pin capacitance (all inputs/outputs) CIN, COUT 10 pF VCC = 5.0V (Note 1); TA = 25°C, FCLK = 1 MHz 2
Operating current, write ICC write 0.1 3 mA VCC = 5.5V, SCL = 400 kHz 2
Operating current, read ICC read 0.05 400 μA 2
Standby current (Industrial) ICCS 0.01 1 μA SDA = SCL = VCC = 5.5V, A0, A1, A2, WP = VSS (Industrial) 2
Clock frequency FCLK 100 kHz 1.7V ≤ VCC < 2.5V 3
Clock frequency FCLK 400 kHz 2.5V ≤ VCC ≤ 5.5V 3
Clock high time THIGH 4000 ns 1.7V ≤ VCC < 2.5V 3
Clock high time THIGH 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Clock low time TLOW 4700 ns 1.7V ≤ VCC < 2.5V 3
Clock low time TLOW 1300 ns 2.5V ≤ VCC ≤ 5.5V 3
SDA and SCL rise time TR 1000 ns 1.7V ≤ VCC < 2.5V (Note 1) 3
SDA and SCL rise time TR 300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) 3
SDA and SCL fall time TF 300 ns (Note 1) 3
Start condition hold time THD:STA 4000 ns 1.7V ≤ VCC < 2.5V 3
Start condition hold time THD:STA 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Start condition setup time TSU:STA 4700 ns 1.7V ≤ VCC < 2.5V 3
Start condition setup time TSU:STA 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Data input hold time THD:DAT 0 ns 3
Data input setup time TSU:DAT 250 ns 1.7V ≤ VCC < 2.5V 3
Data input setup time TSU:DAT 100 ns 2.5V ≤ VCC ≤ 5.5V 3
Stop condition setup time TSU:STO 4000 ns 1.7 V ≤ VCC < 2.5V 3
Stop condition setup time TSU:STO 600 ns 2.5 V ≤ VCC ≤ 5.5V 3
WP setup time TSU:WP 4000 ns 1.7V ≤ VCC < 2.5V 3
WP setup time TSU:WP 600 ns 2.5V ≤ VCC ≤ 5.5V 3
WP hold time THD:WP 4700 ns 1.7V ≤ VCC < 2.5V 3
WP hold time THD:WP 1300 ns 2.5V ≤ VCC ≤ 5.5V 3
Output valid from clock TAA 3500 ns 1.7V ≤ VCC < 2.5V (Note 2) 3
Output valid from clock TAA 900 ns 2.5V ≤ VCC ≤ 5.5V (Note 2) 3
Bus free time TBUF 4700 ns 1.7V ≤ VCC < 2.5V 3
Bus free time TBUF 1300 ns 2.5V ≤ VCC ≤ 5.5V 3
Output fall time from VIH minimum to VIL maximum TOF 250 ns CB ≤ 100 pF (Note 1) 3
Input filter spike suppression (SDA and SCL pins) TSP 50 ns Notes 1 and 3 3
Write cycle time (byte or page) TWC 5 ms 3
Endurance 1e+06 cycles 25°C (Note 4) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead 27

CAD (KiCad official)

  • Symbol: 24AA32AFT-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 24aa32aft-i-etched.step / 24aa32aft-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 24aa32aft-i.step / 24aa32aft-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (30 pp, sha256 3f59b9f70b94e1b1, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF