# 24AA32A-I

**Tudi** · EEPROM · DIP-8

24AA32A-I from Tudi, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input hard-wired to set bit A0 of the device address; it is compared to the address bits and is internally biased low if left floating. |
| 2 | A1 | input | Device address input hard-wired to set bit A1 of the device address, allowing up to eight devices on one bus; it is internally biased low if left floating. |
| 3 | A2 | input | Device address input hard-wired to set bit A2 of the device address, allowing up to eight devices on one bus; it is internally biased low if left floating. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Open-drain bidirectional serial data pin, normally pulled high by an external resistor, which may be wire-OR'ed with other open-drain or open-collector devices; data changes only while SCL is low. |
| 6 | SCL | input | Serial clock input: data is clocked into the device on the SCL positive edge and clocked out on the negative edge. |
| 7 | WP | input | Write Protect input: at GND normal read/write operation is allowed, and at VCC the full 32K array is write-protected. |
| 8 | VCC | power_in | Power supply, specified from +1.7V to +5.5V for operation at 400 kHz (+2.5V to +5.5V for 1 MHz). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Tudi |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Low Level | VOL2 |  |  | 0.4 | V | VCC=5.0V, IOL=3.0mA | 9 |
| Output Low Level | VOL1 |  |  | 0.2 | V | VCC=1.7V, =0.15mA | 9 |
| Input High Level | VIH1 | 0.7 |  | 0.3 | V | VCC=1.7V to 5.5V | 9 |
| Input Low Level | VIL1 | -0.3 |  | 0.3 | V | VCC=1.7V to 5.5V | 9 |
| Output Leakage Current | ILO |  | 0.05 | 1 | μA | VOUT=VCC or VSS | 9 |
| Input Leakage Current | ILI |  | 0.1 | 1 | μA | VIN=VCC or VSS | 9 |
| Supply Current (standby) | ICCS |  | 0.03 | 0.5 | μA | VCC=5.0V | 9 |
| Supply Current (write) | ICC2 |  | 0.28 | 0.5 | mA | VCC=5.0V, WRITE at 400KHZ | 9 |
| Supply Current (read) | ICC1 |  | 0.14 | 0.3 | mA | VCC=5.0V, READ at 400KHZ | 9 |
| Input Capacitance (A0,A1,A2,SCL) | CIN |  |  | 6 | pF | VIN=0V | 9 |
| Input/Output Capacitance (SDA) | CI/O |  |  | 8 | pF | =0V | 9 |
| Data Out Hold Time | DH | 50 |  |  | ns | 1.7V≤VCC<2.5V | 10 |
| Stop Setup Time | Su:STO | 0.6 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Stop Setup Time | Su:STO | 0.25 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Input Fall Time | F |  |  | 0.3 | μs | 1.7V≤VCC<2.5V | 10 |
| Input Fall Time | F |  |  | 0.12 | μs | 2.5V≤VCC<5.5V | 10 |
| Input Rise Time | R |  |  | 0.3 | μs | 1.7V≤VCC<2.5V | 10 |
| Input Rise Time | R |  |  | 0.12 | μs | 2.5V≤VCC<5.5V | 10 |
| Data in Setup Time | SU:DAT | 100 |  |  | ns | 1.7V≤VCC<2.5V | 10 |
| Data In Hold Time | HD:DAT | 0 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Start Setup Time | SU:STA | 0.6 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Start Setup Time | SU:STA | 0.25 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Start Hold Time | HD:STA | 0.6 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Start Hold Time | HD:STA | 0.25 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Time the bus must be free before a new transmission can start | tBUF | 1.3 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Time the bus must be free before a new transmission can start | tBUF | 0.5 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Clock Low to Data Out Valid | AA |  |  | 0.9 | μs | 1.7V≤VCC<2.5V | 10 |
| Clock Low to Data Out Valid | AA |  |  | 0.45 | μs | 2.5V≤VCC<5.5V | 10 |
| Noise Suppression Time | I |  |  | 50 | ns | 1.7V≤VCC<2.5V | 10 |
| Clock Pulse Width High | HIGH | 0.6 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Clock Pulse Width High | HIGH | 0.26 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Clock Pulse Width Low | LOW | 1.3 |  |  | μs | 1.7V≤VCC<2.5V | 10 |
| Clock Pulse Width Low | LOW | 0.5 |  |  | μs | 2.5V≤VCC<5.5V | 10 |
| Clock Frequency, SCL | SCL |  |  | 400 | kHz | 1.7V≤VCC<2.5V | 10 |
| Clock Frequency, SCL | SCL |  |  | 1000 | kHz | 2.5V≤VCC<5.5V | 10 |
| Write Cycle Time | tWR |  | 1.9 | 3 | ms | 1.7V≤VCC<2.5V | 10 |
| Endurance |  | 1 |  |  | M Write Cycle | 5.0V, 25℃, Byte Mode | 10 |
| DC supply voltage |  | -0.3 |  | 6.5 | V |  | 9 |
| Input / Output voltage |  | -0.3 |  |  | V | Min GND-0.3V; max printed as VCC+0.3V | 9 |
| Storage temperature |  | -65 |  | 150 | ℃ |  | 9 |
| Supply voltage | VCC | 1.7 |  | 5.5 | V | @400kHz; VCC=+2.5V to +5.5V @1MHz | 9 |
| Operating ambient temperature | TA | -40 |  | 85 | ℃ | 24LC32/24AA32 (-I, no E1/E0 suffix) | 9 |

## CAD (KiCad official)

- Symbol: `24AA32A-I`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `24aa32a-i-etched.step` / `24aa32a-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `24aa32a-i.step` / `24aa32a-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Tudi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604434806621564928) (17 pp, sha256 `85ee3c73e7c96cdb`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/24aa32a-i-datasheet.pdf)