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24AA256T-I

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Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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24AA256T-I

Microchip Tech · EEPROM · SOIC-8

24AA256T-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input User-configurable chip address input that must be hard-wired or driven to VCC or VSS (logic 1 or 0) before normal device operation.
2 A1 input User-configurable chip address input that must be connected to VCC or VSS, or driven to logic 0 or 1 before normal operation when controlled by a microcontroller.
3 A2 input User-configurable chip address input that must be connected to VCC or VSS, or driven to logic 0 or 1 before normal operation when controlled by a microcontroller.
4 VSS power_in Ground reference for the device.
5 SDA bidirectional Open-drain serial data pin that requires a pull-up resistor to VCC (typically 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz), and may change only while SCL is low.
6 SCL input Serial clock input used to synchronize data transfer to and from the device.
7 WP input Write-protect input that must be tied to VSS (writes enabled) or VCC (writes inhibited, reads unaffected).
8 VCC power_in Supply voltage pin; +1.7V to 5.5V for the 24AA256.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH 0.7 V 2
Low-level input voltage VIL 0.3 V VCC ≥ 2.5V 2
Low-level input voltage VIL 0.2 V VCC < 2.5V 2
Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) VHYS 0.05 V VCC ≥ 2.5V (Note) 2
Low-level output voltage VOL 0.4 V IOL = 3.0 mA @ VCC = 4.5V 2
Input leakage current ILI -1 1 uA VIN = VSS or VCC, WP = VSS 2
Output leakage current ILO -1 1 uA VOUT = VSS or VCC 2
Pin capacitance (all inputs/outputs) CIN, COUT 10 pF VCC = 5.0V (Note); TA = 25°C, FCLK = 1 MHz 2
Read operating current ICC 400 uA VCC = 5.5V, SCL = 400 kHz 2
Write operating current ICC 3 mA VCC = 5.5V 2
Standby current ICCS 1.5 uA TA = -40°C to +85°C; SCL = SDA = VCC = 5.5V; A0, A1, A2, WP = VSS 2
Standby current ICCS 1 uA TA = -40°C to +85°C; SCL = SDA = VCC = 3.6V; A0, A1, A2, WP = VSS 2
Clock frequency FCLK 100 kHz 1.7V ≤ VCC ≤ 2.5V 3
Clock frequency FCLK 400 kHz 2.5V ≤ VCC ≤ 5.5V 3
Clock high time THIGH 4000 ns 1.7V ≤ VCC ≤ 2.5V 3
Clock high time THIGH 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Clock low time TLOW 4700 ns 1.7V ≤ VCC ≤ 2.5V 3
Clock low time TLOW 1300 ns 2.5V ≤ VCC ≤ 5.5V 3
SDA and SCL rise time (Note 1) TR 1000 ns 1.7V ≤ VCC ≤ 2.5V 3
SDA and SCL rise time (Note 1) TR 300 ns 2.5V ≤ VCC ≤ 5.5V 3
SDA and SCL fall time (Note 1) TF 300 ns All except, 24FC256 3
Start condition hold time THD:STA 4000 ns 1.7V ≤ VCC ≤ 2.5V 3
Start condition hold time THD:STA 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Start condition setup time TSU:STA 4700 ns 1.7V ≤ VCC ≤ 2.5V 3
Start condition setup time TSU:STA 600 ns 2.5V ≤ VCC ≤ 5.5V 3
Data input hold time THD:DAT 0 ns (Note 2) 3
Data input setup time TSU:DAT 250 ns 1.7V ≤ VCC ≤ 2.5V 3
Data input setup time TSU:DAT 100 ns 2.5V ≤ VCC ≤ 5.5V 3
Stop condition setup time TSU:STO 4000 ns 1.7V ≤ VCC ≤ 2.5V 3
Stop condition setup time TSU:STO 600 ns 2.5V ≤ VCC ≤ 5.5V 3
WP setup time TSU:WP 4000 ns 1.7V ≤ VCC ≤ 2.5V 3
WP setup time TSU:WP 600 ns 2.5V ≤ VCC ≤ 5.5V 3
WP hold time THD:WP 4700 ns 1.7V ≤ VCC ≤ 2.5V 3
WP hold time THD:WP 1300 ns 2.5V ≤ VCC ≤ 5.5V 3
Output valid from clock (Note 2) TAA 3500 ns 1.7 V ≤ VCC ≤ 2.5V 4
Output valid from clock (Note 2) TAA 900 ns 2.5 V ≤ VCC ≤ 5.5V 4
Bus free time: Time the bus must be free before a new transmission can start TBUF 4700 ns 1.7V ≤ VCC ≤ 2.5V 4
Bus free time: Time the bus must be free before a new transmission can start TBUF 1300 ns 2.5V ≤ VCC ≤ 5.5V 4
Output fall time from VIH minimum to VIL maximum TOF 250 ns CB ≤ 100 pF; All except 24FC256 (Note 1) 4
Input filter spike suppression (SDA and SCL pins) TSP 50 ns All except, 24FC256 (Notes 1 and 3) 4
Write cycle time (byte or page) TWC 5 ms 4
Endurance 1e+06 cycles Page mode, 25°C, 5.5V (Note 4) 4
All inputs and outputs w.r.t. VSS -0.6 V w.r.t. VSS; printed upper limit is VCC + 1.0V (not numeric) 2
Storage temperature -65 150 °C 2
Ambient temperature with power applied -40 125 °C 2
ESD protection on all pins 4 kV 2
Supply voltage (VCC) range, 24AA256 VCC 1.7 5.5 V 24AA256 device 1
Ambient operating temperature, Industrial (I) TA -40 85 °C Industrial (I) temperature grade 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead 39

CAD (KiCad official)

  • Symbol: 24AA256T-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 24aa256t-i-etched.step / 24aa256t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 24aa256t-i.step / 24aa256t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (42 pp, sha256 baed9ce6a87b8033, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF