# 23S05E-1HDCGI

**RENESAS** · Clock Generators / Frequency Synthesizers / PLL · SOIC-8

23S05E-1HDCGI from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | input | Input reference clock, 5 Volt tolerant input with weak pull down; the PLL locks to this clock. |
| 2 | CLK2 | output | Output clock with weak pull down on the output. |
| 3 | CLK1 | output | Output clock with weak pull down on the output. |
| 4 | GND | power_in | Ground. |
| 5 | CLK3 | output | Output clock with weak pull down on the output. |
| 6 | VDD | power_in | 3.3V supply, operating range 3 V to 3.6 V. |
| 7 | CLK4 | output | Output clock with weak pull down on the output. |
| 8 | CLKOUT | output | Output clock with internal PLL feedback taken from this pin; weak pull down on the output. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8 |
| Category | Clock and Timing |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage Range | VDD | -0.5 |  | 4.6 | V |  | 2 |
| Input Voltage Range (REF) | VI | -0.5 |  | 5.5 | V | REF | 2 |
| Input Voltage Range (except REF) | VI | -0.5 |  |  | V | upper limit printed as VDD+0.5 | 2 |
| Input Clamp Current | IIK | -50 |  |  | mA | VI < 0 | 2 |
| Continuous Output Current | IO | -50 |  | 50 | mA | VO = 0 to VDD | 2 |
| VDD or GND Continuous Current |  | -100 |  | 100 | mA |  | 2 |
| Maximum Power Dissipation |  |  |  | 0.7 | W | TA = 55°C, in still air | 2 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 2 |
| Operating Industrial Temperature Range |  | -40 |  | 85 | °C |  | 2 |
| Supply Voltage | VDD | 3 |  | 3.6 | V | Industrial | 4 |
| Operating Temperature (Ambient) | TA | -40 |  | 85 | °C | Industrial | 4 |
| Load Capacitance | CL |  |  | 30 | pF | < 100MHz | 4 |
| Load Capacitance | CL |  |  | 10 | pF | 100MHz - 200MHz | 4 |
| Input Capacitance | CIN |  |  | 7 | pF |  | 4 |
| Input LOW Voltage Level | VIL |  |  | 0.8 | V |  | 4 |
| Input HIGH Voltage Level | VIH | 2 |  |  | V |  | 4 |
| Input LOW Current | IIL |  |  | 50 | µA | VIN = 0V | 4 |
| Input HIGH Current | IIH |  |  | 100 | µA | VIN = VDD | 4 |
| Output LOW Voltage | VOL |  |  | 0.4 | V | High Drive IOL = 12mA (-1H) | 4 |
| Output HIGH Voltage | VOH | 2.4 |  |  | V | High Drive IOH = -12mA (-1H) | 4 |
| Power Down Current | IDD_PD |  |  | 25 | µA | REF = 0MHz | 4 |
| Supply Current | IDD |  |  | 35 | mA | Unloaded Outputs at 66.66MHz | 4 |
| Output Frequency | t1 | 10 |  | 200 | MHz | 10pF Load | 5 |
| Output Frequency | t1 | 10 |  | 100 | MHz | 30pF Load | 5 |
| Duty Cycle = t2 ÷ t1 |  | 40 | 50 | 60 | % | Measured at 1.4V, FOUT = 66.66MHz | 5 |
| Duty Cycle = t2 ÷ t1 |  | 45 | 50 | 55 | % | Measured at 1.4V, FOUT <50MHz | 5 |
| Rise Time | t3 |  |  | 1.5 | ns | Measured between 0.8V and 2V | 5 |
| Fall Time | t4 |  |  | 1.5 | ns | Measured between 0.8V and 2V | 5 |
| Output to Output Skew | t5 |  |  | 250 | ps | All outputs equally loaded | 5 |
| Delay, REF Rising Edge to CLKOUT Rising Edge | t6 | -350 | 0 | 350 | ps | Measured at VDD/2 | 5 |
| Device-to-Device Skew | t7 |  | 0 | 700 | ps | Measured at VDD/2 on the CLKOUT pins of devices | 5 |
| Output Slew Rate | t8 | 1 |  |  | V/ns | Measured between 0.8V and 2V using Test Circuit #2 | 5 |
| Cycle-to-Cycle Jitter, pk-pk | tJ |  |  | 200 | ps | Measured at 66.66MHz, loaded outputs | 5 |
| PLL Lock Time | tLOCK |  |  | 1 | ms | Stable power supply, valid clock presented on REF pin | 5 |

## CAD (KiCad official)

- Symbol: `23S05E-1HDCGI`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `23s05e-1hdcgi-etched.step` / `23s05e-1hdcgi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `23s05e-1hdcgi.step` / `23s05e-1hdcgi.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/23s05e-1hdcgi-datasheet.pdf) (9 pp, sha256 `77c88bca2a38b372`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/23s05e-1hdcgi-datasheet.pdf)