component
23LCV512-I
Public Made by Adomby adom
Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| 23lcv512-i-etched.glb | 1d ago |
| 23lcv512-i-etched.step | 1d ago |
| 23lcv512-i-hero.glb | 1d ago |
| 23lcv512-i-hero.overlay.json | 1d ago |
| 23lcv512-i.glb | 1d ago |
| 23lcv512-i.kicad_mod | 1d ago |
| 23lcv512-i.kicad_sym | 1d ago |
| 23lcv512-i.lbr | 1d ago |
| 23lcv512-i.step | 1d ago |
| package.json | 1d ago |
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| README.md | 1d ago |
23LCV512-I
Microchip Tech · Pre-ordered Chips · SOIC-8
23LCV512-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode, and a low level is required after power-up before any sequence. |
| 2 | SO/SIO1 | bidirectional | Serial data output in SPI mode (shifted out after the falling clock edge, high-impedance when deselected) and SIO1 in SDI dual mode. |
| 3 | NC | unconnected | No connect. |
| 4 | VSS | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in SPI mode (instructions, addresses and data latched on the rising SCK edge) and SIO0 in SDI dual mode. |
| 6 | SCK | input | Serial clock input (up to 20 MHz) that synchronizes communication; SI is latched on the rising edge and SO updates after the falling edge. |
| 7 | VBAT | power_in | External backup supply input (1.4V to 3.6V) that maintains SRAM data when VCC falls below VTRIP (1.6V to 2.0V); connect to VSS if unused. |
| 8 | VCC | power_in | Power supply, 2.5V to 5.5V operating range (6.5V absolute maximum). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2.5 | 5.5 | V | 23LCV512 | 2 | |
| Low-level output voltage | VOL | 0.2 | V | IOL = 1 mA | 2 | ||
| Low-level input voltage (lower bound) | VIL | -0.3 | V | 23LCV512; upper limit printed as 0.10xVCC | 2 | ||
| Input leakage current | ILI | -1 | 1 | µA | CS = VCC, VIN = VSS OR VCC | 2 | |
| Output leakage current | ILO | -1 | 1 | µA | CS = VCC, VOUT = VSS OR VCC | 2 | |
| Read operating current | ICC | 3 | 10 | mA | FCLK = 20 MHz; SO = O, 5.5V | 2 | |
| Standby current | ICCS | 4 | 10 | µA | CS = VCC = 5.5V, Inputs tied to VCC or VSS | 2 | |
| Input capacitance | CINT | 7 | pF | VCC = 0V, f = 1 MHz, Ta = 25°C (Note 1) | 2 | ||
| VBAT change over | VTRIP | 1.6 | 1.8 | 2 | V | Typical at Ta = 25°C (Note 1) | 2 |
| VBAT voltage range | VBAT | 1.4 | 3.6 | V | (Note 1) | 2 | |
| RAM data retention voltage | VDR | 1 | V | (Note 2) | 2 | ||
| VBAT current | IBAT | 1 | µA | Typical at 2.5V, Ta = 25°C (Note 1) | 2 | ||
| Input/output voltage w.r.t. VSS (lower bound) | -0.3 | V | All inputs and outputs w.r.t. VSS; upper limit printed as VCC +0.3V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature under bias | -40 | 85 | °C | 2 | |||
| Operating temperature (Industrial) | TA | -40 | 85 | °C | Industrial (I) | 2 | |
| Clock frequency | FCLK | 20 | MHz | 3 | |||
| CS setup time | TCSS | 25 | ns | 3 | |||
| CS hold time | TCSH | 50 | ns | 3 | |||
| CS disable time | TCSD | 25 | ns | 3 | |||
| Data setup time | Tsu | 10 | ns | 3 | |||
| Data hold time | THD | 10 | ns | 3 | |||
| CLK rise time | TR | 20 | ns | Note 1 | 3 | ||
| CLK fall time | TF | 20 | ns | Note 1 | 3 | ||
| Clock high time | THI | 25 | ns | 3 | |||
| Clock low time | TLO | 25 | ns | 3 | |||
| Clock delay time | TCLD | 25 | ns | 3 | |||
| Output valid from clock low | TV | 25 | ns | 3 | |||
| Output hold time | THO | 0 | ns | Note 1 | 3 | ||
| Output disable time | TDIS | 20 | ns | 3 |
CAD (KiCad official)
- Symbol:
23LCV512-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
23lcv512-i-etched.step/23lcv512-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);23lcv512-i.step/23lcv512-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (30 pp, sha256
27f4bb236e30c587, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).