component
23LC512-I
Public Made by Adomby adom
Microchip Tech SRAM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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23LC512-I
Microchip Tech · SRAM · TSSOP-8
23LC512-I from Microchip Tech, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode with SO in high-impedance; a low level is required after power-up before any sequence. |
| 2 | SO/SIO1 | bidirectional | Serial data output in SPI mode (data shifted out after the falling clock edge, high-impedance when deselected) and SIO1 in SDI/SQI modes. |
| 3 | SIO2 | bidirectional | SQI mode data pin SIO2 (NC in SPI/SDI mode, where the datasheet says pin 3 should not be left floating). |
| 4 | VSS | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in SPI mode (instructions, addresses and data latched on the rising clock edge) and SIO0 in SDI/SQI modes. |
| 6 | SCK | input | Serial clock input that synchronizes communication; inputs are latched on the rising edge and SO updates after the falling edge, up to 20 MHz (16 MHz for E-temp). |
| 7 | HOLD/SIO3 | bidirectional | Hold input that pauses a serial sequence when pulled low (must be held high when unused; not available in SQI mode), or SIO3 in SQI mode. |
| 8 | VCC | power_in | Power supply, 2.5V to 5.5V for 23LC512 (absolute maximum 6.5V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2.5 | 5.5 | V | 23LC512 | 2 | |
| Low-level input voltage (min only) | VIL | -0.3 | V | 23LC512; max is 0.1 VCC | 2 | ||
| Low-level output voltage | VOL | 0.2 | V | IOL = 1 mA | 2 | ||
| Input leakage current | ILI | -1 | 1 | µA | CS = VCC, VIN = VSS OR VCC | 2 | |
| Output leakage current | ILO | -1 | 1 | µA | CS = VCC, VOUT = VSS OR VCC | 2 | |
| Read operating current | ICC | 3 | 10 | mA | FCLK = 20 MHz; SO = O, 5.5V | 2 | |
| Standby current | ICCS | 4 | 10 | µA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, I-Temp | 2 | |
| Input capacitance | CINT | 7 | pF | VCC = 5.0V, f = 1 MHz, TA = 25°C | 2 | ||
| RAM data retention voltage | VDR | 1 | V | 2 | |||
| Clock frequency | FCLK | 20 | MHz | I-Temp | 3 | ||
| CS setup time | TCSS | 25 | ns | I-Temp | 3 | ||
| CS hold time | TCSH | 50 | ns | 3 | |||
| CS disable time | TCSD | 25 | ns | I-Temp | 3 | ||
| Data setup time | Tsu | 10 | ns | 3 | |||
| Data hold time | THD | 10 | ns | 3 | |||
| CLK rise time | TR | 20 | ns | Note 1 | 3 | ||
| CLK fall time | TF | 20 | ns | Note 1 | 3 | ||
| Clock high time | THI | 25 | ns | I-Temp | 3 | ||
| Clock low time | TLO | 25 | ns | I-Temp | 3 | ||
| Clock delay time | TCLD | 25 | ns | I-Temp | 3 | ||
| Output valid from clock low | TV | 25 | ns | I-Temp | 3 | ||
| Output hold time | THO | 0 | ns | Note 1 | 3 | ||
| Output disable time | TDIS | 20 | ns | 3 | |||
| HOLD setup time | THS | 10 | ns | 3 | |||
| HOLD hold time | THH | 10 | ns | 3 | |||
| HOLD low to output High-Z | THZ | 10 | ns | 3 | |||
| HOLD high to output valid | THV | 50 | ns | 3 | |||
| Input/output voltage w.r.t. VSS (min only) | -0.3 | V | All inputs and outputs w.r.t. VSS; max is VCC +0.3V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature under bias | -40 | 125 | °C | 2 | |||
| Operating temperature, Industrial | TA | -40 | 85 | °C | Industrial (I) | 2 |
CAD (KiCad official)
- Symbol:
23LC512-I - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
23lc512-i-etched.step/23lc512-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);23lc512-i.step/23lc512-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (32 pp, sha256
6969e2794a4312d3, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 23LC512-I
**Microchip Tech** · SRAM · TSSOP-8
23LC512-I from Microchip Tech, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select input: a low level selects the device, a high level deselects it and forces Standby mode with SO in high-impedance; a low level is required after power-up before any sequence. |
| 2 | SO/SIO1 | bidirectional | Serial data output in SPI mode (data shifted out after the falling clock edge, high-impedance when deselected) and SIO1 in SDI/SQI modes. |
| 3 | SIO2 | bidirectional | SQI mode data pin SIO2 (NC in SPI/SDI mode, where the datasheet says pin 3 should not be left floating). |
| 4 | VSS | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in SPI mode (instructions, addresses and data latched on the rising clock edge) and SIO0 in SDI/SQI modes. |
| 6 | SCK | input | Serial clock input that synchronizes communication; inputs are latched on the rising edge and SO updates after the falling edge, up to 20 MHz (16 MHz for E-temp). |
| 7 | HOLD/SIO3 | bidirectional | Hold input that pauses a serial sequence when pulled low (must be held high when unused; not available in SQI mode), or SIO3 in SQI mode. |
| 8 | VCC | power_in | Power supply, 2.5V to 5.5V for 23LC512 (absolute maximum 6.5V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2.5 | | 5.5 | V | 23LC512 | 2 |
| Low-level input voltage (min only) | VIL | -0.3 | | | V | 23LC512; max is 0.1 VCC | 2 |
| Low-level output voltage | VOL | | | 0.2 | V | IOL = 1 mA | 2 |
| Input leakage current | ILI | -1 | | 1 | µA | CS = VCC, VIN = VSS OR VCC | 2 |
| Output leakage current | ILO | -1 | | 1 | µA | CS = VCC, VOUT = VSS OR VCC | 2 |
| Read operating current | ICC | | 3 | 10 | mA | FCLK = 20 MHz; SO = O, 5.5V | 2 |
| Standby current | ICCS | | 4 | 10 | µA | CS = VCC = 5.5V, Inputs tied to VCC or VSS, I-Temp | 2 |
| Input capacitance | CINT | | | 7 | pF | VCC = 5.0V, f = 1 MHz, TA = 25°C | 2 |
| RAM data retention voltage | VDR | | 1 | | V | | 2 |
| Clock frequency | FCLK | | | 20 | MHz | I-Temp | 3 |
| CS setup time | TCSS | 25 | | | ns | I-Temp | 3 |
| CS hold time | TCSH | 50 | | | ns | | 3 |
| CS disable time | TCSD | 25 | | | ns | I-Temp | 3 |
| Data setup time | Tsu | 10 | | | ns | | 3 |
| Data hold time | THD | 10 | | | ns | | 3 |
| CLK rise time | TR | | | 20 | ns | Note 1 | 3 |
| CLK fall time | TF | | | 20 | ns | Note 1 | 3 |
| Clock high time | THI | 25 | | | ns | I-Temp | 3 |
| Clock low time | TLO | 25 | | | ns | I-Temp | 3 |
| Clock delay time | TCLD | 25 | | | ns | I-Temp | 3 |
| Output valid from clock low | TV | | | 25 | ns | I-Temp | 3 |
| Output hold time | THO | 0 | | | ns | Note 1 | 3 |
| Output disable time | TDIS | | | 20 | ns | | 3 |
| HOLD setup time | THS | 10 | | | ns | | 3 |
| HOLD hold time | THH | 10 | | | ns | | 3 |
| HOLD low to output High-Z | THZ | 10 | | | ns | | 3 |
| HOLD high to output valid | THV | | | 50 | ns | | 3 |
| Input/output voltage w.r.t. VSS (min only) | | -0.3 | | | V | All inputs and outputs w.r.t. VSS; max is VCC +0.3V | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 2 |
| Operating temperature, Industrial | TA | -40 | | 85 | °C | Industrial (I) | 2 |
## CAD (KiCad official)
- Symbol: `23LC512-I`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `23lc512-i-etched.step` / `23lc512-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `23lc512-i.step` / `23lc512-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/23lc512-i-datasheet.pdf) (32 pp, sha256 `6969e2794a4312d3`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/23lc512-i-datasheet.pdf)