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2309A-1DCGI

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RENESAS Clock Generators / Frequency Synthesizers / PLL, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing2309a-1dcgifactory-2.0.0extractor-text

Verified 2309A-1DCGI

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 2309A-1DCGI · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 9-page datasheet
  • ✓distributor: lcsc C1536014, digikey 6690-2309A-1DCGI-ND, mouser 972-2309A-1DCGI
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-creaqfld/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 2309a-1dcgi.kicad_sym✓ 2309a-1dcgi.kicad_mod✓ 2309a-1dcgi.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16h ago
viewers 2309a-1dcgi: viewers · Ray 16h ago
2309a-1dcgi-etched.glb Publish 0.1.0 · Ray 16h ago
2309a-1dcgi-etched.step 2309a-1dcgi: factory component page (tier=lcsc) · Ray 16h ago
2309a-1dcgi-hero.glb 2309a-1dcgi: hero GLB from the etched model (keeps the MPN mark) · Ray 16h ago
2309a-1dcgi-hero.overlay.json Publish 0.1.0 · Ray 16h ago
2309a-1dcgi.glb Publish 0.1.0 · Ray 16h ago
2309a-1dcgi.kicad_mod Publish 0.1.0 · Ray 16h ago
2309a-1dcgi.kicad_sym Publish 0.1.0 · Ray 16h ago
2309a-1dcgi.lbr Publish 0.1.0 · Ray 16h ago
2309a-1dcgi.step Publish 0.1.0 · Ray 16h ago
package.json Publish 0.1.0 · Ray 16h ago
page.json Set visibility: public · Ray 16h ago
README.md Publish 0.1.0 · Ray 16h ago
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray 16h ago

2309A-1DCGI

RENESAS · Clock Generators / Frequency Synthesizers / PLL · SOIC-16

2309A-1DCGI from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Input reference clock to which the on-chip PLL locks; this is a 5 V tolerant input.
2 CLKA1 output Output clock for bank A; the datasheet specifies a weak pull-down on all outputs.
3 CLKA2 output Output clock for bank A; the datasheet specifies a weak pull-down on all outputs.
4 VDD power_in 3.3V supply pin; pins 4 and 13 are both VDD.
5 GND power_in Ground pin; pins 5 and 12 are both GND.
6 CLKB1 output Output clock for bank B; the datasheet specifies a weak pull-down on all outputs.
7 CLKB2 output Output clock for bank B; the datasheet specifies a weak pull-down on all outputs.
8 S2 input Select input bit 2, which has a weak pull-up and sets the output source and PLL shut-down mode together with S1.
9 S1 input Select input bit 1, which has a weak pull-up and sets the output source and PLL shut-down mode together with S2.
10 CLKB3 output Output clock for bank B; the datasheet specifies a weak pull-down on all outputs.
11 CLKB4 output Output clock for bank B; the datasheet specifies a weak pull-down on all outputs.
12 GND power_in Ground pin; pins 5 and 12 are both GND.
13 VDD power_in 3.3V supply pin; pins 4 and 13 are both VDD.
14 CLKA3 output Output clock for bank A; the datasheet specifies a weak pull-down on all outputs.
15 CLKA4 output Output clock for bank A; the datasheet specifies a weak pull-down on all outputs.
16 CLKOUT output Output clock that also serves as the internal PLL feedback pin; it has a weak pull-down, and its loading adjusts the input-output delay.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-16
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range (absolute maximum) VDD -0.5 4.6 V 2
Input Voltage Range (REF) (absolute maximum) VI -0.5 5.5 V Input Voltage Range (REF) 2
Input Voltage Range except REF (absolute maximum) VI -0.5 V Except REF; upper limit printed as VDD+0.5 2
Input Clamp Current IIK -50 mA VI < 0 2
Continuous Output Current IO -50 50 mA VO = 0 to VDD 2
VDD or GND Continuous Current -100 100 mA 2
Maximum Power Dissipation (still air) 0.7 W TA = 55°C, in still air 2
Storage Temperature Range TSTG -65 150 °C 2
Input LOW Voltage Level VIL 0.8 V 4
Input HIGH Voltage Level VIH 2 V 4
Input LOW Current IIL 50 µA VIN = 0V 4
Input HIGH Current IIH 100 µA VIN = VDD 4
Output LOW Voltage (Standard Drive) VOL 0.4 V Standard Drive IOL = 8mA 4
Output HIGH Voltage (Standard Drive) VOH 2.4 V Standard Drive IOH = -8mA 4
Power Down Current IDD_PD 25 µA REF = 0MHz (S2 = S1 = H) 4
Supply Current IDD 35 mA Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND 4
Supply Voltage (industrial operating) VDD 3 3.6 V 4
Operating Temperature (industrial) TA -40 85 °C Ambient temperature 4
Load Capacitance CL 30 pF < 100MHz 4
Load Capacitance CL 10 pF 100MHz - 133MHz 4
Input Capacitance CIN 7 pF 4
Output Frequency t1 10 133 MHz 10pF Load 5
Output Frequency t1 10 100 MHz 30pF Load 5
Duty Cycle (t2 / t1) 40 50 60 % Measured at 1.4V, FOUT = 66.66MHz 5
Rise Time t3 2.5 ns Measured between 0.8V and 2V 5
Fall Time t4 2.5 ns Measured between 0.8V and 2V 5
Output to Output Skew t5 250 ps All outputs equally loaded 5
Delay, REF Rising Edge to CLKOUT Rising Edge t6A -350 0 350 ps Measured at VDD/2 5
Delay, REF Rising Edge to CLKOUT Rising Edge (PLL bypass) t6B 1 5 8.7 ns Measured at VDD/2 in PLL bypass mode (IDT2309A only) 5
Device-to-Device Skew t7 0 700 ps Measured at VDD/2 on the CLKOUT pins of devices 5
Cycle-to-Cycle Jitter tJ 200 ps Measured at 66.66MHz, loaded outputs 5
PLL Lock Time tLOCK 1 ms Stable power supply, valid clock presented on REF pin 5

CAD (KiCad official)

  • Symbol: 2309A-1DCGI
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 2309a-1dcgi-etched.step / 2309a-1dcgi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 2309a-1dcgi.step / 2309a-1dcgi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (9 pp, sha256 70f4c462b1aaed5f, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF