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π220N61

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2Pai Semi Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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π220N61

2Pai Semi · Digital Isolators · SOIC-16-300mil

π220N61 from 2Pai Semi, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND1 power_in Ground 1, the ground reference for isolator Side 1.
2 NC unconnected No connect.
3 VDD1 power_in Supply voltage for isolator Side 1 (3.0 V to 5.5 V), bypassed with 0.1 µF to 10 µF to GND1.
4 NC unconnected No connect.
5 SDA1 bidirectional Open-drain serial data input/output, side 1, with 3.5 mA max sink current and pull-up resistor required.
6 SCL1 bidirectional Open-drain serial clock input/output, side 1, with 3.5 mA max sink current and pull-up resistor required.
7 GND1 power_in Ground 1, the ground reference for isolator Side 1.
8 GND1 power_in Ground 1, the ground reference for isolator Side 1.
9 GND2 power_in Ground 2, the ground reference for isolator Side 2.
10 NC unconnected No connect.
11 SCL2 bidirectional Open-drain serial clock input/output, side 2, with 35 mA max sink current and pull-up resistor required.
12 SDA2 bidirectional Open-drain serial data input/output, side 2, with 35 mA max sink current and pull-up resistor required.
13 NC unconnected No connect.
14 VDD2 power_in Supply voltage for isolator Side 2 (3.0 V to 5.5 V), bypassed with 0.1 µF to 10 µF to GND2.
15 NC unconnected No connect.
16 GND2 power_in Ground 2, the ground reference for isolator Side 2.

Key specifications

Parameter Value
Manufacturer 2Pai Semi
Package SOIC-16-300mil
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (absolute maximum) VDD1-GND1, VDD2-GND2 -0.5 7 V 2
Average Output Current SDA1/SCL1 IO1 -20 20 mA 2
Average Output Current SDA2/SCL2 IO2 -100 100 mA 2
Storage Temperature TST -55 150 °C 2
Maximum junction temperature TJ(MAX) 150 °C 2
Supply Voltage VDDx 3 5.5 V 2
Low-level input voltage, side 1 VIL1 0 0.47 V 2
Output current, side 1 IOL1 0.5 3.5 mA 3
Output current, side 2 IOL2 0.5 35 mA 3
Capacitive load, side 1 C1 40 pF 3
Capacitive load, side 2 C2 400 pF 3
Operating frequency fMAX 2 MHz 3
Ambient Operating Temperature TA -40 125 °C 3
Voltage input threshold low, SDA1 and SCL1 VILT1 470 510 570 mV 3
Voltage input threshold high, SDA1 and SCL1 VIHT1 540 580 630 mV 3
Voltage input hysteresis, side 1 VHYST1 50 70 mV VIHT1 -VILT1 3
Low-level output voltage, SDA1 and SCL1 VOL1 650 720 800 mV 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 3
VOL1 to VIHT1 threshold difference ΔVOIT1 60 120 mV 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 3
Low-level output voltage, SDA2 and SCL2 VOL2 0.4 V 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA 3
Input leakage currents /IIN/ 0.01 10 µA VSDA1, VSCL1 = VDD1; VSDA2, VSCL2 = VDD2 4
VDDx Undervoltage Rising Threshold VDDxUV+ 2.45 2.75 2.95 V 4
VDDx Undervoltage Falling Threshold VDDxUV− 2.3 2.6 2.8 V 4
VDDx Undervoltage Hysteresis VDDxUVH 0.15 V 4
π220N61 Quiescent current IDD1 @5V IDD1 (Q) 1.7 2.4 mA VSDA1, VSCL1 = GND1; 5VDC 4
π220N61 Quiescent current IDD2 @5V IDD2 (Q) 1.4 2.1 mA VSDA2, VSCL2 = GND2; 5VDC 4
π220N61 Quiescent current IDD1 @5V IDD1 (Q) 1.5 2.3 mA VSDA1, VSCL1 = VDD1; 5VDC 4
π220N61 Quiescent current IDD2 @5V IDD2 (Q) 1.2 1.8 mA VSDA2, VSCL2 = VDD2; 5VDC 4
π220N61 Quiescent current IDD1 @3.3V IDD1 (Q) 1.5 2.3 mA VSDA1, VSCL1 = GND1; 3.3VDC 4
π220N61 Quiescent current IDD2 @3.3V IDD2 (Q) 1.2 1.8 mA VSDA2, VSCL2 = GND2; 3.3VDC 4
Output Fall Time SDA1, SCL1 tf1 10 18 30 ns 0.9 VDD1 to 0.9 V; R1 = 1430 Ω, C1 = 40 pF, @ 5VDC supply 4
Output Fall Time SDA1, SCL1 tf1 9 16 28 ns R1 = 953 Ω, C1 = 40 PF; @ 3.3VDC supply 4
Output Fall Time SDA1, SCL1 tf1 6 11 18 ns 0.7 VDD1 to 0.3 VDD1; R1 = 1430 Ω, C1 = 40 pF, @ 5VDC supply 4
Output Fall Time SDA1, SCL1 tf1 6 10 16 ns R1 = 953 Ω, C1 = 40 PF; @ 3.3VDC supply 4
Output Fall Time SDA2, SCL2 tf2 22 36 45 ns 0.9VDD2 to 0.4V; R2 = 143 Ω, C2 = 400 pF, @ 5VDC supply 4
Output Fall Time SDA2, SCL2 tf2 20 31 42 ns R2 = 95.3 Ω, C2 = 400 pF; @ 3.3VDC supply 4
Output Fall Time SDA2, SCL2 tf2 9 16 26 ns 0.7 VDD2 to 0.3 VDD2; R2 = 143 Ω, C2 = 400 pF, @ 5VDC supply 4
Output Fall Time SDA2, SCL2 tf2 8 14 23 ns R2 = 95.3 Ω, C2 = 400 pF; @ 3.3VDC supply 5
Low-to-High Propagation Delay, Side 1 to Side 2 tpLH1-2 45 68 ns R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
Low-to-High Propagation Delay, Side 1 to Side 2 tpLH1-2 38 57 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
High-to-Low Propagation Delay, Side 1 to Side 2 tPHL1-2 67 100 ns R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
High-to-Low Propagation Delay, Side 1 to Side 2 tPHL1-2 64 96 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
Pulse Width Distortion 1-2 PWD1-2 22 32 ns R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
Pulse Width Distortion 1-2 PWD1-2 26 39 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
Low-to-High Propagation Delay, Side 2 to Side 1 tPLH2-1 44 62 ns R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
Low-to-High Propagation Delay, Side 2 to Side 1 tPLH2-1 42 56 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
High-to-Low Propagation Delay, Side 2 to Side 1 tPHL2-1 52 78 ns R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
High-to-Low Propagation Delay, Side 2 to Side 1 tPHL2-1 57 86 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
Pulse Width Distortion 2-1 PWD2-1 8 16 ns R1 = 1430 Ω, R2 = 143 Ω, C1,2 = 10 pF; @ 5VDC supply 5
Pulse Width Distortion 2-1 PWD2-1 15 30 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
Round-trip propagation delay on Side 1 tLOOP1 104 156 ns 0.4 V to 0.3 × VDD1; R1 = 1430 Ω, R2 = 143 Ω, C1, C2 = 10 pF; @ 5VDC supply 5
Round-trip propagation delay on Side 1 tLOOP1 88 132 ns R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF; @ 3.3VDC supply 5
Common-Mode Transient Immunity CMTI 120 kV/µs VIN = VDDx or 0V, VCM = 1000 V. 5
ESD (HBM) ESD -6 6 kV 5
IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-11, each π220N61/π221N61 is proof tested by applying an insulation test voltage ≥ 1800 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking br 6

CAD (KiCad official)

  • Symbol: π220N61
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: 220n61-etched.step / 220n61-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 220n61.step / 220n61.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 2Pai Semi datasheet (15 pp, sha256 ec5b830abb81f738, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF