component
1EDN8511B
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Infineon Technologies Gate Drivers, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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1EDN8511B
Infineon Technologies · Gate Drivers · SOT-23-6
1EDN8511B from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage with an operating range of 4.5 V to 20 V. |
| 2 | OUT_SRC | output | Low-impedance driver output with source capability. |
| 3 | OUT_SNK | output | Low-impedance driver output with sink capability. |
| 4 | GND | power_in | Ground reference for the driver. |
| 5 | IN- | input | Inverting logic input; if IN- is high or left open, OUT is driven low (see Table 4). |
| 6 | IN+ | input | Non-inverting logic input; if IN+ is low or left open, OUT is driven low (see Table 4). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Motor Driver ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VVDD | -0.3 | 22 | V | 10 | ||
| Voltage at pins IN+, IN- | VIN | -10 | 22 | V | 10 | ||
| Voltage at pins OUT, OUT_SRC, OUT_SNK | VOUT | -0.3 | V | Max printed as VVDD+0.3 V; voltage spikes from reverse current peaks allowed (Note 1) | 10 | ||
| Voltage at pins OUT, OUT_SRC, OUT_SNK, repetitive pulse | VOUT | -2 | V | Repetitive pulse < 200ns; max printed as VVDD+2 V | 10 | ||
| Reverse current peak at pins OUT, OUT_SRC/OUT_SNK (sink) | ISNK_rev | -5 | A | Apk < 500 ns | 10 | ||
| Reverse current peak at pins OUT, OUT_SRC/OUT_SNK (source) | ISRC_rev | 5 | A | Apk < 500 ns | 10 | ||
| Junction temperature | TJ | -40 | 150 | °C | 10 | ||
| Storage temperature | TS | -55 | 150 | °C | 10 | ||
| ESD capability (CDM) | VESD | 1.5 | kV | Charged Device Mode (CDM), ANSI/ESDA/JEDEC JS-002 | 10 | ||
| ESD capability (HBM) | VESD | 2.5 | kV | Human Body Model (HBM), ANSI/ESDA/JEDEC JS-001 | 10 | ||
| Supply voltage | VVDD | 4.5 | 20 | V | Min defined by UVLO | 12 | |
| Logic input voltage | VIN | -5 | 20 | V | 12 | ||
| Junction temperature (operating) | TJ | -40 | 150 | °C | Continuous operation above 125 °C may reduce life time | 12 | |
| UVLO turn on threshold (standard and superjunction version) | UVLOon | 7.4 | 8 | 8.6 | V | 12 | |
| UVLO turn off threshold (standard and superjunction version) | UVLOoff | 6.5 | 7 | 7.5 | V | 12 | |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | 13 | |
| Input voltage threshold for transition HL | VINL | 0.8 | 1 | 1.2 | V | 13 | |
| High level (sourcing) output resistance | Ron_SRC | 0.42 | 0.85 | 1.46 | Ω | ISRC = 50 mA | 13 |
| Low level (sinking) output resistance | Ron_SNK | 0.18 | 0.35 | 0.64 | Ω | ISNK = 50 mA | 13 |
| Input to output propagation delay (turn-on) | TPDON | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Input to output propagation delay (turn-off) | TPDOFF | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Rise time | TRISE | 6.5 | 11 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 | |
| Minimum input pulse width that changes output state | TPW | 6 | 10 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 | |
| Junction-to-ambient thermal resistance (PG-SOT23-6-2) | RthJA25 | 170 | K/W | PG-SOT23-6-2, Tamb=25°C | 10 | ||
| Junction-to-case (top) thermal resistance (PG-SOT23-6-2) | RthJC25 | 81 | K/W | PG-SOT23-6-2, Tamb=25°C | 10 | ||
| Junction-to-board thermal resistance (PG-SOT23-6-2) | RthJB25 | 52 | K/W | PG-SOT23-6-2, Tamb=25°C | 10 | ||
| Characterization parameter junction-case (top) (PG-SOT23-6-2) | ΨthJC25 | 14 | K/W | PG-SOT23-6-2, Tamb=25°C | 10 | ||
| Characterization parameter junction-board (PG-SOT23-6-2) | ΨthJB25 | 51 | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
CAD (KiCad official)
- Symbol:
1EDN8511B - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
1edn8511b-etched.step/1edn8511b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1edn8511b.step/1edn8511b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (27 pp, sha256
72868b5acc4db261, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 1EDN8511B
**Infineon Technologies** · Gate Drivers · SOT-23-6
1EDN8511B from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage with an operating range of 4.5 V to 20 V. |
| 2 | OUT_SRC | output | Low-impedance driver output with source capability. |
| 3 | OUT_SNK | output | Low-impedance driver output with sink capability. |
| 4 | GND | power_in | Ground reference for the driver. |
| 5 | IN- | input | Inverting logic input; if IN- is high or left open, OUT is driven low (see Table 4). |
| 6 | IN+ | input | Non-inverting logic input; if IN+ is low or left open, OUT is driven low (see Table 4). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Motor Driver ICs |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VVDD | -0.3 | | 22 | V | | 10 |
| Voltage at pins IN+, IN- | VIN | -10 | | 22 | V | | 10 |
| Voltage at pins OUT, OUT_SRC, OUT_SNK | VOUT | -0.3 | | | V | Max printed as VVDD+0.3 V; voltage spikes from reverse current peaks allowed (Note 1) | 10 |
| Voltage at pins OUT, OUT_SRC, OUT_SNK, repetitive pulse | VOUT | -2 | | | V | Repetitive pulse < 200ns; max printed as VVDD+2 V | 10 |
| Reverse current peak at pins OUT, OUT_SRC/OUT_SNK (sink) | ISNK_rev | | | -5 | A | Apk < 500 ns | 10 |
| Reverse current peak at pins OUT, OUT_SRC/OUT_SNK (source) | ISRC_rev | | | 5 | A | Apk < 500 ns | 10 |
| Junction temperature | TJ | -40 | | 150 | °C | | 10 |
| Storage temperature | TS | -55 | | 150 | °C | | 10 |
| ESD capability (CDM) | VESD | | | 1.5 | kV | Charged Device Mode (CDM), ANSI/ESDA/JEDEC JS-002 | 10 |
| ESD capability (HBM) | VESD | | | 2.5 | kV | Human Body Model (HBM), ANSI/ESDA/JEDEC JS-001 | 10 |
| Supply voltage | VVDD | 4.5 | | 20 | V | Min defined by UVLO | 12 |
| Logic input voltage | VIN | -5 | | 20 | V | | 12 |
| Junction temperature (operating) | TJ | -40 | | 150 | °C | Continuous operation above 125 °C may reduce life time | 12 |
| UVLO turn on threshold (standard and superjunction version) | UVLOon | 7.4 | 8 | 8.6 | V | | 12 |
| UVLO turn off threshold (standard and superjunction version) | UVLOoff | 6.5 | 7 | 7.5 | V | | 12 |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | | 13 |
| Input voltage threshold for transition HL | VINL | 0.8 | 1 | 1.2 | V | | 13 |
| High level (sourcing) output resistance | Ron_SRC | 0.42 | 0.85 | 1.46 | Ω | ISRC = 50 mA | 13 |
| Low level (sinking) output resistance | Ron_SNK | 0.18 | 0.35 | 0.64 | Ω | ISNK = 50 mA | 13 |
| Input to output propagation delay (turn-on) | TPDON | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Input to output propagation delay (turn-off) | TPDOFF | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Rise time | TRISE | | 6.5 | 11 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Minimum input pulse width that changes output state | TPW | | 6 | 10 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 13 |
| Junction-to-ambient thermal resistance (PG-SOT23-6-2) | RthJA25 | | 170 | | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
| Junction-to-case (top) thermal resistance (PG-SOT23-6-2) | RthJC25 | | 81 | | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
| Junction-to-board thermal resistance (PG-SOT23-6-2) | RthJB25 | | 52 | | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
| Characterization parameter junction-case (top) (PG-SOT23-6-2) | ΨthJC25 | | 14 | | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
| Characterization parameter junction-board (PG-SOT23-6-2) | ΨthJB25 | | 51 | | K/W | PG-SOT23-6-2, Tamb=25°C | 10 |
## CAD (KiCad official)
- Symbol: `1EDN8511B`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `1edn8511b-etched.step` / `1edn8511b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `1edn8511b.step` / `1edn8511b.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835562170413056) (27 pp, sha256 `72868b5acc4db261`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/1edn8511b-datasheet.pdf)