component
1EDN7550B
Public Made by Adomby adom
Infineon Technologies Gate Drive ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown1EDN7550B
Infineon Technologies · Gate Drive ICs · SOT-23-6
1EDN7550B from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN- | input | Negative differential input, connected to controller ground via a resistor (typically 33 kΩ), with input voltage range -7 V to 6 V operating. |
| 2 | GND | power_in | Ground and negative gate drive voltage ("off" state) of the driver. |
| 3 | IN+ | input | Positive differential input, connected to the PWM output of the controller via a resistor (typically 33 kΩ), with input voltage range -7 V to 6 V operating. |
| 4 | VDD | power_in | Positive supply voltage (positive gate drive voltage, "on" state), operating range 4.5 V to 20 V with absolute maximum 22 V. |
| 5 | OUT_SRC | output | Driver source output, low-impedance switch to VDD (4 A / 0.85 Ω). |
| 6 | OUT_SNK | output | Driver sink output, low-impedance switch to GND (8 A / 0.35 Ω). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Power Management ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| UVLO turn on threshold | UVLOon | 3.9 | 4.2 | 4.5 | V | 9 | |
| UVLO threshold hysteresis | UVLOhys | 0.25 | 0.3 | 0.35 | V | 9 | |
| Propagation delay turn-on | tPDon | 38 | 45 | 55 | ns | CL = 200 pF | 10 |
| Propagation delay turn-off | tPDoff | 38 | 45 | 55 | ns | CL = 200 pF | 10 |
| Rise time | trise | 6.5 | 15 | ns | CL = 1.8 nF | 10 | |
| Fall time | tfall | 4.5 | 15 | ns | CL = 1.8 nF | 10 | |
| Rise time | trise | 1 | 5 | ns | CL = 200 pF | 10 | |
| Fall time | tfall | 1 | 5 | ns | CL = 200 pF | 10 | |
| Supply voltage | VDD | -0.3 | 22 | V | Voltage between VDD to GND | 7 | |
| Voltage at pins IN+ and IN- | VIN | -10 | 10 | V | 7 | ||
| Voltage at pin OUT_SRC (DC) | VOUT_SRC | -24 | 0.3 | V | OUT = low; referred to VDD pin, DC | 7 | |
| Voltage at pin OUT_SRC (transient) | VOUT_SRC | -24 | 2 | V | OUT = low; referred to VDD pin < 200 ns | 7 | |
| Voltage at pin OUT_SNK (DC) | VOUT_SNK | -0.3 | 24 | V | OUT = high; referred to GND pin, DC | 7 | |
| Voltage at pin OUT_SNK (transient) | VOUT_SNK | -2 | 24 | V | OUT = high, referred to GND pin < 200 ns | 7 | |
| Peak reverse current at OUT_SRC (negative) | ISRC_rev | -5 | A | < 500 ns | 7 | ||
| Peak reverse current at OUT_SRC (positive) | ISRC_rev | 5 | A | < 500 ns | 7 | ||
| Junction temperature | Tj | -40 | 150 | °C | 7 | ||
| Storage temperature | TS | -55 | 150 | °C | 7 | ||
| ESD capability HBM | VESD_HBM | 2 | kV | Human Body Model (HBM) | 7 | ||
| ESD capability CDM | VESD_CDM | 1 | kV | Charged Device Model (CDM) | 7 | ||
| Supply voltage | VDD | 4.5 | 20 | V | Min defined by UVLO | 9 | |
| Voltage at pins IN+ and IN- | VIN | -7 | 6 | V | 9 | ||
| Junction temperature | Tj | -40 | 150 | °C | 9 | ||
| Thermal resistance junction-ambient | RthJA25 | 165.1 | K/W | SOT23 package | 8 | ||
| Thermal resistance junction-case (top) | RthJC25 | 79.9 | K/W | SOT23 package | 8 | ||
| Thermal resistance junction-board | RthJB25 | 65.2 | K/W | SOT23 package | 8 | ||
| Characterization parameter junction-case (top) | ΨthJC25 | 14 | K/W | SOT23 package | 8 | ||
| Characterization parameter junction-board | ΨthJB25 | 51 | K/W | SOT23 package | 8 | ||
| VDD quiescent current, OUT high | IVDDh | 1.1 | mA | OUT = high | 9 | ||
| VDD quiescent current, OUT low | IVDDl | 0.9 | mA | OUT = low | 9 | ||
| UVLO turn off threshold | UVLOoff | 3.9 | V | 9 | |||
| Input threshold transition LH | ΔVRinH | 1.7 | V | Independent of VDD; Rin1/Rin2 = 33 kΩ | 10 | ||
| Input threshold transition HL | ΔVRinL | 1.5 | V | Independent of VDD; Rin1/Rin2 = 33 kΩ | 10 | ||
| Total input resistance on each leg | Rin1 / Rin2 | 36 | kΩ | Rin1/Rin2 = 33 kΩ | 10 | ||
| High-level (sourcing) output resistance | Ron_SRC | 0.85 | Ω | ISRC = 50 mA | 10 | ||
| Sourcing output current | ISRC_pk | 4 | A | 10 | |||
| Low-level (sinking) output resistance | Ron_SNK | 0.35 | Ω | ISNK = 50 mA | 10 | ||
| Sinking output current | ISNK_pk | -8 | A | 10 |
CAD (KiCad official)
- Symbol:
1EDN7550B - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
1edn7550b-etched.step/1edn7550b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1edn7550b.step/1edn7550b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (27 pp, sha256
3a81fe6f4396c8cf, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).