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1EDN7512B

Public Made by Adom

by adom

Infineon Technologies Gate Drivers, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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1EDN7512B

Infineon Technologies · Gate Drivers · SOT-23-5

1EDN7512B from Infineon Technologies, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage with an operating range of 4.5 V to 20 V (minimum defined by UVLO).
2 GND power_in Ground reference pin for the driver.
3 IN+ input Non-inverting logic input; if IN+ is low or left open, OUT is driven low.
4 IN- input Inverting logic input; if IN- is high or left open, OUT is driven low.
5 OUT output Low-impedance driver output with sink capability; this package has a shorted source/sink output.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOT-23-5
Category Motor Driver ICs
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive supply voltage VVDD -0.3 22 V 12
Voltage at pins IN+, IN- VIN -10 22 V 12
Voltage at pins OUT (Note 1: voltage spikes from reverse current peaks allowed) VOUT -0.3 V Note 1; max printed as VVDD+0.3 V 12
Voltage at pins OUT, repetitive pulse VOUT -2 V Repetitive pulse < 200ns (Note 2); max printed as VVDD+0.3 V 12
Reverse current peak at pins OUT, OUT_SRC/OUT_SNK ISNK_rev / ISRC_rev -5 5 A Apk < 500 ns 12
Junction temperature TJ -40 150 °C 12
Storage temperature TS -55 150 °C 12
ESD capability, Charged Device Model VESD 1.5 kV Charged Device Mode (CDM), JESD22-C101 12
ESD capability, Human Body Model VESD 2.5 kV Human Body Model (HBM), JESD22-A114 12
Supply voltage operating range VVDD 4.5 20 V Min defined by UVLO 14
Logic input voltage VIN -5 20 V 14
Junction temperature operating range TJ -40 150 °C Note 1: continuous operation above 125 °C may reduce life time 14
UVLO turn on threshold (logic level MOSFET version, 4.2 V) UVLOon 3.9 4.2 4.5 V 14
UVLO turn off threshold (logic level MOSFET version, 4.2 V) UVLOoff 3.6 3.9 4.2 V 14
UVLO threshold hysteresis (logic level MOSFET version) UVLOhys 0.3 V 14
Input voltage threshold for transition LH VINH 1.9 2.1 2.3 V 15
Input voltage threshold for transition HL VINL 0.8 1 1.2 V 15
Input pull up resistor (inputs with initial high logic level) RIN H 400 kΩ Inputs with initial high logic level 15
Input pull down resistor (inputs with initial low logic level) RIN L 100 kΩ Inputs with initial low logic level 15
High Level (Sourcing) Output Resistance Ron_SRC 0.42 0.85 1.46 Ω ISRC = 50 mA 15
Low Level (Sinking) Output Resistance Ron_SNK 0.18 0.35 0.64 Ω ISNK = 50 mA 15
High Level (Sourcing) Output Current (active limited by design at approx. 5.2 Apk; not production tested) ISRC_peak 4 A Verified by design/characterization 15
Low Level (Sinking) Output Current (active limited by design at approx. -10.4 Apk; not production tested) ISNK_Peak -8 A Verified by design/characterization 15
Input to output propagation delay, turn-on TPDON 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V 15
Input to output propagation delay, turn-off TPDOFF 15 19 25 ns CLOAD= 1.8 nF, VVDD= 12 V 15
Rise time (verified by design, not 100% tested) TRISE 6.5 11 ns CLOAD= 1.8 nF, VVDD= 12 V 15
Fall time (verified by design, not 100% tested) TFAll 4.5 9 ns CLOAD= 1.8 nF, VVDD= 12 V 15
Minimum input pulse width that changes output state TPW 6 10 ns CLOAD= 1.8 nF, VVDD= 12 V 15
VDD quiescent current, OUT high IVDDqu1 0.4 mA OUT = high, VVDD= 12 V 14
VDD quiescent current, OUT low IVDDqu2 0.37 mA OUT = low, VVDD= 12 V 14
Thermal resistance junction-ambient, PG-SOT23-5-1 RthJA25 180 K/W Tamb=25°C; JESD51-7 high-K board, natural convection 13
Thermal resistance junction-case (top), PG-SOT23-5-1 RthJC25 76 K/W Tamb=25°C 13
Thermal resistance junction-board, PG-SOT23-5-1 RthJB25 60 K/W Tamb=25°C 13
Thermal resistance junction-bottom (heat sink), PG-SOT23-5-1 RthJB25 16 K/W Tamb=25°C 13
Characterization parameter junction-case (top), PG-SOT23-5-1 ΨthJB25 14 K/W Tamb=25°C 13
Characterization parameter junction-board, PG-SOT23-5-1 ΨthJB25 52 K/W Tamb=25°C 13

CAD (KiCad official)

  • Symbol: 1EDN7512B
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: 1edn7512b-etched.step / 1edn7512b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 1edn7512b.step / 1edn7512b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (28 pp, sha256 4ff6078c815e0c87, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF