component
1EDN7512
Public Made by Adomby adom
Tokmas Gate Drivers, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown1EDN7512
Tokmas · Gate Drivers · TSOT-23-5
1EDN7512 from Tokmas, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply of the gate driver (4.5 V to 24 V per the recommended operating conditions), which must be decoupled by a ceramic capacitor with 0.1 µF and 1 µF or 10 µF recommended. |
| 2 | GND | power_in | Power ground, which must be soldered directly to the ground planes for improved thermal performance and electrical contact. |
| 3 | IN+ | input | Non-inverting TTL-compatible logic input that is held low when floating; apply the PWM signal here for non-inverting operation, or connect it to VDD for inverting operation. |
| 4 | IN- | input | Inverting TTL-compatible logic input that is held low when floating; connect it to GND for non-inverting operation, or apply the PWM signal here for inverting operation. |
| 5 | OUT | output | Gate driver output capable of 4 A peak source and 4 A peak sink current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tokmas |
| Package | TSOT-23-5 |
| Category | Motor Driver ICs |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range (IN+, IN-) | VIN+,IN- | -5 | 26 | V | 2 | ||
| OUT voltage | OUT | -0.3 | 26 | V | 2 | ||
| VDD voltage | VDD | -0.3 | 26 | V | 2 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 2 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 2 | ||
| Supply voltage range | VDD | 4.5 | 24 | V | 3 | ||
| Input voltage range | VIN+,IN- | -5 | 24 | V | 3 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 3 | ||
| ESD Human Body Model (HBM), all pins | VESD | -2 | 2 | kV | HBM per ANSI-JEDEC-JS-001-2014, all pins | 3 | |
| ESD Charged Device Model (CDM), all pins | VESD | -1 | 1 | kV | CDM per ANSI-JEDEC-JS-002-2014, all pins | 3 | |
| Operating supply voltage | VDD | 4.5 | 24 | V | 4 | ||
| Input UVLO threshold, VDD rising | VDD_UVLO | 4.2 | 4.5 | V | VDD rising | 4 | |
| Input+ logic high threshold | VIN+ | 2.1 | 2.4 | V | 4 | ||
| Input+ logic low threshold | VIN+ | 0.8 | 1 | V | 4 | ||
| Input- logic high threshold | VIN-_H | 2.1 | 2.4 | V | 4 | ||
| Input- logic low threshold | VIN-_L | 0.8 | 1 | V | 4 | ||
| Output rising time | TR | 9 | 20 | ns | CLoad=1nF | 4 | |
| Output falling time | TF | 6 | 20 | ns | CLoad=1nF | 4 | |
| IN+ to output propagation delay, rising edge | TD_IN+ | 12 | 25 | ns | 4 | ||
| IN+ to output propagation delay, falling edge | TD_IN+ | 12 | 25 | ns | 4 | ||
| IN- to output propagation delay, rising | TD_IN- | 12 | 25 | ns | 4 | ||
| IN- to output propagation delay, falling | TD_IN- | 12 | 25 | ns | 4 | ||
| Minimum input pulse width | TMIN_ON | 20 | 30 | ns | CLoad=1nF | 4 | |
| Input UVLO hysteresis | 300 | mV | 4 | ||||
| Quiescent current | IQ | 38 | uA | IN+=IN-=GND, VDD=3.5V | 4 | ||
| Quiescent current | IQ | 120 | uA | IN+=IN-=GND, VDD=12V | 4 | ||
| Input+ hysteresis | VIN+_Hys | 1.1 | V | 4 | |||
| Input- hysteresis | VIN-_Hys | 1.1 | V | 4 | |||
| Output high voltage (only PMOS ON) | VDD_VOH | 150 | mV | IOUT=10mA | 4 | ||
| Output low voltage | VOL | 10 | mV | IOUT=10mA | 4 | ||
| Output sink/source peak current | ISINK/SRC | 4 | A | CLoad=10nF, Fsw=1kHz | 4 | ||
| Output pull-high resistance (only PMOS ON) | ROH | 8.5 | Ω | IOUT= - 10mA | 4 | ||
| Output pull-low resistance | ROL | 0.6 | Ω | IOUT= 10mA | 4 | ||
| Thermal shutdown threshold | TSD | 170 | °C | TJ rising | 4 | ||
| Thermal shutdown hysteresis | 25 | °C | 4 | ||||
| Junction to ambient thermal resistance | RθJA | 89 | °C/W | TSOT23-5 package | 3 | ||
| Junction to case thermal resistance | RθJC | 39 | °C/W | TSOT23-5 package | 3 |
CAD (KiCad official)
- Symbol:
1EDN7512 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
1edn7512-etched.step/1edn7512-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1edn7512.step/1edn7512.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Tokmas datasheet (16 pp, sha256
81a467b43b61225d, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).