# 1EDN6550BXTSA1

**Infineon Technologies** · Gate Drive ICs · SOT-23-6

1EDN6550BXTSA1 from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN- | input | Negative differential input, connected to controller PWM or ground via input resistor (see Chapter 6); input voltage range -10 V to 10 V. |
| 2 | GND | power_in | Ground, negative gate drive voltage ("off" state voltage). |
| 3 | IN+ | input | Positive differential input, connected to controller PWM or ground via input resistor (see Chapter 6); input voltage range -10 V to 10 V. |
| 4 | VDD | power_in | Supply voltage, positive gate drive voltage ("on" state voltage), absolute maximum 22 V relative to GND. |
| 5 | OUT_SRC | output | Driver source output, low-impedance switch to VDD (4 A/0.85 Ω). |
| 6 | OUT_SNK | output | Driver sink output, low-impedance switch to GND (8 A/0.35 Ω). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Power Management |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 4.5 |  | 20 | V | Min defined by UVLO | 10 |
| Voltage at pins IN+ and IN- | VIN | -7 |  | 6 | V |  | 10 |
| Junction temperature | TJ | -40 |  | 150 | °C | Continuous operation above 125°C may reduce life time | 10 |
| UVLO turn on threshold | UVLOon | 11.7 | 12.2 | 12.7 | V | 1EDN6550B | 11 |
| UVLO turn off threshold | UVLOoff | 11 | 11.5 |  | V | 1EDN6550B | 11 |
| UVLO threshold hysteresis | UVLOhys | 0.5 | 0.7 | 0.9 | V | 1EDN6550B | 11 |
| Input-to-output propagation delay turn-on | tPDon | 38 | 45 | 55 | ns | CL = 200 pF | 12 |
| Input-to-output propagation delay turn-off | tPDoff | 38 | 45 | 55 | ns | CL = 200 pF | 12 |
| Rise time | trise |  | 6.5 | 15 | ns | CL = 1.8 nF | 12 |
| Fall time | tfall |  | 4.5 | 15 | ns | CL = 1.8 nF | 12 |
| Rise time | trise |  | 1 | 5 | ns | CL = 200 pF | 12 |
| Fall time | tfall |  | 1 | 5 | ns | CL = 200 pF | 12 |
| Supply voltage | VDD | -0.3 |  | 22 | V | Voltage between VDD to GND | 8 |
| Voltage at pins IN+ and IN- | VIN | -10 |  | 10 | V |  | 8 |
| Voltage at pin OUT_SRC | VOUT_SRC | -24 |  | 0.3 | V | OUT = low; referred to VDD pin, DC | 8 |
| Voltage at pin OUT_SRC | VOUT_SRC | -24 |  | 2 | V | OUT = low; referred to VDD pin < 200 ns | 8 |
| Voltage at pin OUT_SNK | VOUT_SNK | -0.3 |  | 24 | V | OUT = high; referred to GND pin, DC | 8 |
| Voltage at pin OUT_SNK | VOUT_SNK | -2 |  | 24 | V | OUT = high, referred to GND pin < 200 ns | 8 |
| Peak reverse current at OUT_SNK | ISNK_rev | -5 |  |  | A | < 500 ns | 8 |
| Peak reverse current at OUT_SRC | ISRC_rev |  |  | 5 | A | < 500 ns | 8 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 8 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 8 |
| ESD capability HBM | VESD_HBM |  |  | 2 | kV | Human Body Model (HBM) | 8 |
| ESD capability CDM | VESD_CDM |  |  | 1 | kV | Charged Device Model (CDM) | 8 |
| Thermal resistance junction-ambient | RthJA25 |  | 165.1 |  | K/W | SOT23-6 | 9 |
| Thermal resistance junction-case (top) | RthJC25 |  | 79.9 |  | K/W | SOT23-6 | 9 |
| Thermal resistance junction-board | RthJB25 |  | 65.2 |  | K/W | SOT23-6 | 9 |
| Characterization parameter junction-case (top) | ΨthJC25 |  | 14 |  | K/W | SOT23-6 | 9 |
| Characterization parameter junction-board | ΨthJB25 |  | 51 |  | K/W | SOT23-6 | 9 |
| VDD quiescent current | IVDDh |  | 1.1 |  | mA | OUT = high VDD = 12 V | 10 |
| VDD quiescent current | IVDDh |  | 1.3 |  | mA | OUT = high VDD = 18 V | 10 |
| VDD quiescent current | IVDDl |  | 0.9 |  | mA | OUT = low VDD = 12 V | 10 |
| VDD quiescent current | IVDDl |  | 1 |  | mA | OUT = low VDD = 18 V | 10 |
| Differential input threshold LH | ∆VRinH |  | 1.7 |  | V | Independent of VDD Rin1 = Rin2 = 33 kΩ | 11 |
| Differential input threshold HL | ∆VRinL |  | 1.5 |  | V | Independent of VDD Rin1 = Rin2 = 33 kΩ | 11 |
| Total input resistance on each leg | Rin1, Rin2 |  | 36 |  | kΩ | Rin1 = Rin2 = 33 kΩ | 11 |
| High-level (sourcing) output resistance | Ron_SRC |  | 0.85 |  | Ω | ISRC = 50 mA | 12 |
| Sourcing output current | ISRC_pk |  | 4 |  | A | VDD = 12 V | 12 |
| Sourcing output current | ISRC_pk |  | 5.2 |  | A | VDD = 18 V | 12 |
| Low-level (sinking) output resistance | Ron_SNK |  | 0.35 |  | Ω | ISNK = 50 mA | 12 |
| Sinking output current | ISNK_pk |  | -8 |  | A | VDD = 12 V | 12 |
| Sinking output current | ISNK_pk |  | -9.4 |  | A | VDD = 18 V | 12 |
| Minimum input pulse width that changes output state | tPW |  | 25 |  | ns | CL = 1.8 nF | 12 |

## CAD (KiCad official)

- Symbol: `1EDN6550BXTSA1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `1edn6550bxtsa1-etched.step` / `1edn6550bxtsa1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `1edn6550bxtsa1.step` / `1edn6550bxtsa1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/1edn6550bxtsa1-datasheet.pdf) (31 pp, sha256 `8a8d4f9a141344fa`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/1edn6550bxtsa1-datasheet.pdf)