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1EDI60N12AF
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Infineon Technologies Gate Drivers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdown1EDI60N12AF
Infineon Technologies · Gate Drivers · SO-8
1EDI60N12AF from Infineon Technologies, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Logic input supply voltage with a 3.3 V to 15 V wide operating range (Table 3 gives an operating range of 3.1 V to 17 V for VCC1). |
| 2 | IN+ | input | Non-inverted driver input (active high) that controls the output when IN- is low, with an internal weak pull-down that favors the off-state and a minimum pulse width to filter noise. |
| 3 | IN- | input | Inverted driver input (active low) that controls the output when IN+ is high, with an internal weak pull-up that favors the off-state and a minimum pulse width to filter noise. |
| 4 | GND1 | power_in | Logic ground and ground connection of the input circuit, to which the input-side voltages are referenced. |
| 5 | VCC2 | power_in | Positive power supply of the output driving circuit, which needs a blocking capacitor placed close to the pin (operating range 10 V to 35 V referenced to GND2 per Table 3). |
| 6 | OUT+ | output | Driver source output that turns on the external MOSFET by switching to VCC2 in the on-state, is turned off at a UVLO event, and can sink approximately 100 mA during turn-off. |
| 7 | OUT- | output | Driver sink output that turns off the external MOSFET by switching to GND2 in the off-state, where an active shut-down keeps the output low during UVLO. |
| 8 | GND2 | power_in | Reference ground of the output driving circuit; in a bipolar supply this pin is connected to the negative supply voltage (e.g. -8 V relative to the MOSFET source in the typical example). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SO-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply output side | VVCC2 | -0.3 | 40 | V | With respect to GND2 | 14 | |
| Positive power supply input side | VVCC1 | -0.3 | 18 | V | 14 | ||
| Logic input voltages (IN+,IN-) | VLogicIN | -0.3 | 18 | V | 14 | ||
| Input to output isolation voltage (GND2) | VISO | -1200 | 1200 | V | 14 | ||
| Junction temperature | TJ | -40 | 150 | °C | 14 | ||
| Storage temperature | TS | -55 | 150 | °C | 14 | ||
| Power dissipation (Input side) | PD, IN | 25 | mW | @TA = 25°C | 14 | ||
| Power dissipation (Output side) | PD, OUT | 400 | mW | @TA = 25°C | 14 | ||
| Thermal resistance (Input side) | RTHJA,IN | 145 | K/W | @TA = 85°C | 14 | ||
| Thermal resistance (Output side) | RTHJA,OUT | 165 | K/W | @TA = 85°C | 14 | ||
| ESD capability | VESD,HBM | 2 | kV | Human Body Model | 14 | ||
| Power supply output side | VVCC2 | 10 | 35 | V | With respect to GND2 | 15 | |
| Power supply input side | VVCC1 | 3.1 | 17 | V | 15 | ||
| Logic input voltages (IN+,IN-) | VLogicIN | -0.3 | 17 | V | 15 | ||
| Switching frequency | fsw | 4 | MHz | Do not exceed max. power dissipation | 15 | ||
| Ambient temperature | TA | -40 | 125 | °C | 15 | ||
| Thermal coefficient, junction-top | Ψth,jt | 4.8 | K/W | @TA = 85°C | 15 | ||
| Common mode transient immunity (CMTI) | /dVISO/dt/ | 100 | kV/µs | @ 1000 V | 15 | ||
| UVLO threshold input chip (rising) | VUVLOH1 | 2.85 | 3.1 | V | 15 | ||
| UVLO threshold input chip (falling) | VUVLOL1 | 2.55 | 2.75 | V | 15 | ||
| UVLO hysteresis input chip (VUVLOH1 - VUVLOL1) | VHYS1 | 90 | 100 | mV | 15 | ||
| UVLO threshold output chip MOSFET supply (rising) | VUVLOH2 | 9.1 | 10 | V | 15 | ||
| UVLO threshold output chip MOSFET supply (falling) | VUVLOL2 | 8 | 8.5 | V | 15 | ||
| UVLO hysteresis output chip (VUVLOH2 - VUVLOL2) | VHYS2 | 550 | 600 | mV | 15 | ||
| IN+,IN- low input voltage (relative to VCC1) | VIN+L, VIN-L | 30 | % of VCC1 | 16 | |||
| IN+,IN- high input voltage (relative to VCC1) | VIN+H, VIN-H | 70 | % of VCC1 | 16 | |||
| IN+,IN- low input voltage | VIN+L, VIN-L | 1.5 | V | 16 | |||
| IN+,IN- high input voltage | VIN+H, VIN-H | 3.5 | V | 16 | |||
| IN- input current | IIN- | 70 | 200 | µA | VIN- = GND1 | 16 | |
| IN+ input current | IIN+ | 70 | 200 | µA | VIN+ = VCC1 | 16 | |
| Quiescent current input chip | IQ1 | 0.65 | 1 | mA | VVCC1 = 5 V, IN+ = High, IN- = Low => OUT = High | 16 | |
| Quiescent current output chip | IQ2 | 1.2 | 2 | mA | VVCC2 = 15 V, IN+ = High, IN- = Low => OUT = High | 16 | |
| High level output peak current | IOUT+,PEAK | 6 | 10 | A | IN+ = High, IN- = Low, VVCC2 = 15 V | 16 | |
| Low level output peak current | IOUT-,PEAK | 6 | 9.4 | A | IN+ = Low, IN- = Low, VVCC2 = 15 V | 16 | |
| Clamping voltage (OUT+) (VOUT - VVCC2) | VCLPout | 0.9 | 1.3 | V | IN+ = High, IN- = Low, OUT = High, IOUT = 500 mA pulse test, tCLPmax = 10 µs | 17 | |
| Input IN to output propagation delay ON | TPDON | 95 | 120 | 142 | ns | CLOAD = 100 pF, VIN+ = 50%, VOUT = 50% @ 25°C | 17 |
| Input IN to output propagation delay OFF | TPDOFF | 105 | 125 | 150 | ns | CLOAD = 100 pF, VIN+ = 50%, VOUT = 50% @ 25°C | 17 |
| Input IN to output propagation delay distortion (TPDOFF - TPDON) | TPDISTO | -15 | 5 | 25 | ns | 17 | |
| Input pulse suppression IN+, IN- | TMININ+, TMININ- | 30 | 40 | ns | 17 | ||
| IN input to output propagation delay ON variation due to temperature | TPDONt | 10 | ns | CLOAD = 100 pF, VIN+ = 50%, VOUT = 50% | 17 | ||
| IN input to output propagation delay OFF variation due to temperature | TPDOFFt | 10 | ns | CLOAD = 100 pF, VIN+ = 50%, VOUT = 50% | 17 | ||
| IN input to output propagation delay distortion variation due to temperature (TPDOFF-TPDON) | TPDISTOt | 4 | ns | CLOAD = 100 pF, VIN+ = 50%, VOUT = 50% | 17 | ||
| Rise time | TRISE | 5 | 10 | 20 | ns | CLOAD = 1 nF, VL 20%, VH 80% | 17 |
| Fall time | TFALL | 4 | 9 | 19 | ns | CLOAD = 1 nF, VL 20%, VH 80% | 17 |
| Active shut down voltage | VACTSD | 2.2 | 2.5 | V | IOUT-/IOUT-,PEAK = 0.1, VCC2 open | 18 |
CAD (KiCad official)
- Symbol:
1EDI60N12AF - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
1edi60n12af-etched.step/1edi60n12af-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1edi60n12af.step/1edi60n12af.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (22 pp, sha256
e151972a8f8433c8, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).