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1ED3321MC12NXUMA1
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Infineon Technologies Gate Drivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdown1ED3321MC12NXUMA1
Infineon Technologies · Gate Drivers · SOIC-16
1ED3321MC12NXUMA1 from Infineon Technologies, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VEE2 | power_in | Negative power supply pin of the output chip; if no negative supply is available, all VEE2 pins must be connected to GND2. |
| 2 | DESAT | input | Desaturation detection input that monitors IGBT VCE and turns the IGBT off when VCE stays above a defined value after the adjustable blanking time (set by an external capacitor) has expired while OUT or OUTH is high. |
| 3 | GND2 | power_in | Reference ground of the output chip. |
| 4 | OUTH | output | Driver charge output that is switched to VCC2 in normal operation and is high impedance during error mode (UVLO, internal error or DESAT) and OFF. |
| 5 | VCC2 | power_in | Positive power supply pin of the output side. |
| 6 | OUTL | output | Driver discharge output that is switched to VEE2 in normal operation and is turned on during error mode (UVLO, internal error or DESAT). |
| 7 | CLAMP | output | Miller clamp that ties the gate to VEE2 after turn-off once the gate voltage falls below VCLAMP (relative to VEE2), designed for a Miller current up to 2 A. |
| 8 | VEE2 | power_in | Negative power supply pin of the output chip; if no negative supply is available, all VEE2 pins must be connected to GND2. |
| 9 | GND1 | power_in | Ground connection of the input side. |
| 10 | IN+ | input | Non-inverting driver input; the power transistor is on when IN+ is high and IN- is low, with a minimum pulse width defined for glitch immunity and an internal pull-down that keeps the output low. |
| 11 | IN- | input | Inverting driver input; the power transistor is on when IN- is low and IN+ is high, with a minimum pulse width defined for glitch immunity and an internal pull-up that keeps the output low. |
| 12 | RDY | output | Open-drain ready output that is high only when both chips are above the UVLO level and the internal chip transmission is faultless. |
| 13 | /FLT | output | Open-drain fault output, low active, that goes low when a desaturation fault of the power transistor occurs. |
| 14 | /RST | input | Reset input, low active: low switches the power transistor off (enable/shutdown) and, held low for time tRST, resets the DESAT fault state; an internal pull-up keeps /FLT released. |
| 15 | VCC1 | power_in | 5 V or 3.3 V power supply pin of the input chip. |
| 16 | GND1 | power_in | Ground connection of the input side. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-16 |
| Category | Motor Driver ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive power supply output side voltage | VVCC2 | -0.3 | 40 | V | 1) in respect to GND2 | 18 | |
| Negative power supply output side voltage | VVEE2 | -22 | 0.3 | V | 1) in respect to GND2 | 18 | |
| Maximum power supply voltage difference output side | Vmax2 | -0.3 | 40 | V | 2) in respect to VEE2 | 18 | |
| Gate driver output difference | VOUTH-OUTL | -40 | 40 | V | 1D3320, 1ED3321, 1ED3322 (as printed) | 18 | |
| Gate driver output current (1ED3321, 1ED3322) | IOUTH, IOUTL | -9 | 9 | A | 3) t = 1 µs on, 5 µs period, limited by max. power dissipation; 4) not production tested | 18 | |
| CLAMP to gate driver output difference | VOUTH-CLAMP, VOUTL-CLAMP | -40 | 40 | V | 1D3320, 1ED3321, 1ED3322 (as printed) | 18 | |
| CLAMP output current | ICLAMP | -4.5 | 4.5 | A | 3) t = 1 µs on, 5 µs period, limited by max. power dissipation; 4) not production tested | 18 | |
| Positive power supply voltage input side | VVCC1 | -0.3 | 7 | V | 5) in respect to GND1 | 18 | |
| Junction temperature | TJ | -40 | 150 | °C | 19 | ||
| Storage temperature | TST | -55 | 150 | °C | 19 | ||
| ESD capability HBM model | VESDHBM | -4 | 4 | kV | HBM model according ANSI/ESDA/JEDEC JS-001 | 19 | |
| Positive power supply output side | VVCC2 | 35 | V | 20 | |||
| Negative power supply output side | VVEE2 | -20 | 0 | V | 1) in respect to GND2 | 20 | |
| Power supply input side | VVCC1 | 5.5 | V | 3) in respect to GND1 | 20 | ||
| Logic input voltages | VLogicIN | -0.3 | V | 3) in respect to GND1 | 20 | ||
| DESAT voltage | VDESAT | -0.3 | V | 1) in respect to GND2 | 20 | ||
| Ambient temperature | TA | -40 | 125 | °C | 20 | ||
| Operating junction temperature | TJop | -40 | 150 | °C | 20 | ||
| Common Mode Transient Immunity | CMTI | -300 | 300 | kV/µs | @ VISO = 1.5 kV; 4) not production tested | 20 | |
| High level output on resistance (1ED3321) | RDSON,H | 0.5 | 0.79 | 1.3 | Ω | IOUTH = 0.1 A | 22 |
| Low level output on resistance (1ED3321) | RDSON,L | 0.35 | 0.51 | 0.85 | Ω | IOUTL = 0.1 A | 22 |
| Low level clamp on resistance | RDSON,CLP | 0.4 | 0.6 | 1 | Ω | IOUTL = 0.1 A | 23 |
| Clamp threshold voltage | VCLAMP | 1.6 | 2.1 | 2.4 | V | in respect to VEE2 | 23 |
| Input IN+, IN-, /RST to output propagation delay on | tPDON | 74 | 80 | 84 | ns | CLOAD = 100 pF, VIN+ = 70 %, VOUT = 20 %, TA = 25 °C | 23 |
| Input IN+, IN-, /RST to output propagation delay off | tPDOFF | 81 | 86 | 92 | ns | CLOAD = 100 pF, VIN+ = 30 %, VOUT = 80 %, TA = 25 °C | 23 |
| Input IN+, IN-, /RST pulse suppression time (filter time) | tINFLT | 29 | 35 | 41 | ns | shorter pulses will not propagate to the output | 23 |
| Blanking capacitor charge current | IDESATC | 438 | 510 | 582 | µA | VVCC2 = 15 V, VVEE2 = GND2, VDESAT-VGND2 = 2 V | 24 |
| Desaturation reference level | VDESATth | 8.5 | 9 | 9.5 | V | VVCC2 = 15 V, in respect to GND2 | 24 |
| Desaturation out slope with capacitive load (1ED3320, 1ED3321) | tDESATOUT_CL_SO | 1 | 3.5 | 6 | us | VVCC2 = 15 V, VVEE2 = 0 V, VOUT = 10 %, COUT = 47 nF, OUTH tied to OUTL, VCLAMP = 5 V | 25 |
| Desaturation low voltage | VDESATL | 0.25 | 0.5 | 0.95 | V | IN+ = Low, IN- = Low, OUT(H,L) = Low, IDESAT = 70 mA | 25 |
| Leading edge blanking | tDESATleb | 280 | 400 | 500 | ns | 25 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | dissipation. The 1ED332xMC12N is conceived to dissipate most of the heat generated through this pins. Figure 16 Reference layout for thermal data (Copper thickness 102 μm) | 30 |
CAD (KiCad official)
- Symbol:
1ED3321MC12NXUMA1 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
1ed3321mc12nxuma1-etched.step/1ed3321mc12nxuma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1ed3321mc12nxuma1.step/1ed3321mc12nxuma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (33 pp, sha256
8b0f42f9805be5a6, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).