# 1ED3125MU12FXUMA1

**Infineon Technologies** · Gate Drive ICs · SOIC-8

1ED3125MU12FXUMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Logic input supply voltage with a 3.3 V up to 15 V wide operating range, referenced to GND1. |
| 2 | IN+ | input | Non-inverted control signal for the driver output, with an internal filter for noise robustness and a weak internal pull-down that favors the off-state. |
| 3 | IN- | input | Inverted control signal for the driver output, with an internal filter for noise robustness and a weak internal pull-up that favors the off-state. |
| 4 | GND1 | power_in | Ground connection of the input circuit. |
| 5 | VCC2 | power_in | Positive power supply pin of the output driving circuit; a blocking capacitor must be placed close to this pin. Operating range is 10 V to 35 V with respect to VEE2. |
| 6 | OUT | output | Combined source and sink output to the external IGBT, switching between VCC2 and VEE2; an active shut-down keeps the output low during an UVLO event. |
| 7 | CLAMP | output | Active Miller clamp output that ties to VEE2 during off-state once the gate voltage drops below 2.0 V referred to VEE2; connect directly to the IGBT gate. |
| 8 | VEE2 | power_in | Reference ground of the output driving circuit, connected to the negative supply in bipolar supply configurations. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input to output offset voltage | VOFFSET |  |  | 2300 | V | VVEE2,max-VVEE2,min with VVEE2,max ≥ VGND1 ≥ VVEE2,min | 11 |
| Power supply output side | VVCC2 | -0.3 |  | 40 | V |  | 11 |
| Power supply input side | VVCC1 | -0.3 |  | 17 | V | VCC1 - GND1 | 11 |
| Logic input voltages (IN+, IN-) | VIN | -0.3 |  | 6.5 | V | IN - GND1 | 11 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 11 |
| Storage temperature | TStg | -55 |  | 150 | °C |  | 11 |
| Power dissipation (input side) | PD,IN |  |  | 100 | mW | TA = 65°C | 11 |
| Power dissipation (output side) | PD,OUT |  |  | 500 | mW | TA = 65°C | 11 |
| Thermal resistance junction to ambient | RthJA,OUT |  |  | 151 | K/W | TA = 85°C 150 mil, 1s0p, PJ = 500 mW | 11 |
| Characterization parameter junction to package top input side | ΨJtop |  |  | 3.3 | K/W |  | 11 |
| ESD robustness human body model | VESD,HBM |  |  | 4 | kV | Human body model | 11 |
| Power supply output side | VVCC2 | 10 |  | 35 | V | With respect to VEE2 | 12 |
| Power supply input side | VVCC1 | 3.1 |  | 15 | V |  | 12 |
| Logic input voltages (IN+, IN-) | VIN | -0.3 |  | 5.5 | V |  | 12 |
| Switching frequency | fSW |  |  | 1 | MHz | PD applies | 12 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 12 |
| Common mode transient immunity | CMTI | -200 |  | 200 | kV/µs | VOFFSET,test = 1500 V | 12 |
| UVLO threshold input side (on) | VUVLOH1 |  |  | 3.1 | V |  | 13 |
| UVLO threshold input side (off) | VUVLOL1 | 2.5 |  |  | V |  | 13 |
| UVLO hysteresis input side | VHYS1 | 0.1 | 0.2 |  | V |  | 13 |
| UVLO threshold output side (off) | VUVLOL2,1 | 10.5 |  |  | V | 1ED3124MU12F, 1ED3125MU12F | 13 |
| UVLO threshold output side (on) | VUVLOH2,1 |  |  | 12.5 | V | 1ED3124MU12F, 1ED3125MU12F | 13 |
| UVLO hysteresis output side | VHYS2 | 0.8 |  |  | V |  | 13 |
| Quiescent current input side | IQ1 |  |  | 1.1 | mA | static, output low | 13 |
| Quiescent current output side | IQ2 |  |  | 2 | mA |  | 13 |
| Start up time | tSTART |  | 2.5 | 20 | µs |  | 13 |
| UVLO detection filter time | tUVLOflt | 50 |  |  | ns |  | 13 |
| Logic low input voltage IN+, IN- | VIN,L |  |  | 1.1 | V |  | 13 |
| Logic high input voltage IN+, IN- | VIN,H | 2.5 |  |  | V |  | 13 |
| Low/high hysteresis IN+, IN- | VIN,HYS | 0.5 | 0.8 |  | V |  | 13 |
| Input current IN+, IN- | IIN |  |  | 100 | µA | VVCC1 = 5 V; VIN ≤ VVCC1 | 13 |
| IN+ pull down resistor | RIN,PD |  | 75 |  | kΩ | to GND1 | 13 |
| IN- pull up resistor | RIN,PU |  | 75 |  | kΩ | ensures high-level detection with unconnected pin | 13 |
| High level output peak current | IOUT,H | 4 | 10 |  | A | VCC2-OUT = 15 V, Output on | 14 |
| High level output on resistance | RDSON,H | 0.26 | 0.5 | 0.85 | Ω | IOUT,H = 0.1 A | 14 |
| Low level output peak current | IOUT,L | 4 | 9 |  | A | OUT-VEE2 = 15 V, Output off | 14 |
| Low level output on resistance | RDSON,L | 0.23 | 0.38 | 0.65 | Ω | IOUT,L = 0.1 A | 14 |
| Low level clamp peak current | ICLAMP,L | 2 | 3 |  | A | VCLAMP = 2.0 V | 14 |
| Low level clamp on resistance | RDSON,CLP | 0.26 | 0.45 | 0.75 | Ω | IOUT,L = 0.1 A | 14 |
| CLAMP threshold voltage | VCLAMP | 1.6 | 2 | 2.4 | V | CLAMP-VEE2 | 14 |
| CLAMP comparator to CLAMP activation delay time | tCLPDLY |  |  | 80 | ns | VCLAMP ≤ 2.0 V | 14 |
| High level output voltage | ΔVOUT,H |  |  | 0.3 | V | VCC2-VOUT,H; IOUT = 20 mA | 14 |
| Low level output voltage | ΔVOUT,L |  |  | 0.1 | V | VCC2-VOUT,H; IOUT = 20 mA | 14 |
| Short circuit clamp voltage between OUT+/CLAMP and VCC2 | VCLP |  |  | 2 | V | Output on, IOUT = 500 mA, t < 10 µs | 14 |
| Input to output propagation delay ON | tPDON | 80 | 90 | 100 | ns | CLOAD = 100 pF, IN turn-on threshold to 10% output on | 15 |
| Input to output propagation delay OFF | tPDOFF | 80 | 90 | 100 | ns | CLOAD = 100 pF, IN turn-off threshold to 90% output off | 15 |
| Input to output propagation delay distortion | tPDISTO | -5 | 0 | 5 | ns | tPDOFF - tPDON | 15 |
| Input pulse suppression time (filter time) | tINFLT | 30 |  |  | ns | shorter pulses will not propagate to the output | 15 |
| Minimum input pulse length | tMININ |  |  | 40 | ns |  | 15 |
| Input to output propagation delay variation due to temperature | tPD,T |  |  | 14 | ns |  | 15 |
| Input to output propagation delay distortion variation due to temperature | tPDISTO,T |  |  | 3 | ns |  | 15 |
| Input to output part to part propagation delay ON variation | /tPDon,P2P/ |  |  | 7 | ns | CLOAD = 100 pF | 15 |
| Rise time | tRISE |  |  | 15 | ns | CLOAD = 100 pF | 15 |
| Fall time | tFALL |  |  | 15 | ns | CLOAD = 100 pF | 15 |
| Rise time | tRISE |  |  | 30 | ns | CLOAD = 1 nF | 15 |
| Fall time | tFALL |  |  | 30 | ns | CLOAD = 1 nF | 15 |
| Active shut down voltage, cold | VACTSD,C |  |  | 1.9 | V | IOUT = 10 mA; VCC2 unsupplied; TA < 20°C | 15 |
| Active shut down voltage, hot | VACTSD,H |  |  | 1.7 | V | IOUT- = 10 mA; VCC2 unsupplied; TA ≥ 20°C | 15 |

## CAD (KiCad official)

- Symbol: `1ED3125MU12FXUMA1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `1ed3125mu12fxuma1-etched.step` / `1ed3125mu12fxuma1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `1ed3125mu12fxuma1.step` / `1ed3125mu12fxuma1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/1ed3125mu12fxuma1-datasheet.pdf) (18 pp, sha256 `21f2abf4da56527c`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/1ed3125mu12fxuma1-datasheet.pdf)