1ED3122MU12HXUMA1

Infineon Technologies · Gate Drive ICs · SOIC-8-300mil

1ED3122MU12HXUMA1 from Infineon Technologies, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC1	power_in	Positive logic supply for the input side with a 3.3 V up to 15 V wide operating range (3.1 V to 15 V operating, 17 V absolute maximum, referred to GND1).
2	IN+	input	Non-inverted driver input (active high) with internal noise filter and weak 75 kΩ pull-down favoring off-state; absolute maximum 6.5 V referred to GND1.
3	IN-	input	Inverted driver input (active low) with internal noise filter and weak 75 kΩ pull-up favoring off-state; absolute maximum 6.5 V referred to GND1.
4	GND1	power_in	Ground connection of the input circuit (logic ground) to which input-side parameters are referred.
5	VEE2	power_in	Reference ground of the output driving circuit, connected to the negative supply in case of a bipolar supply.
6	CLAMP	output	Active Miller clamp output that ties to VEE2 during off-state once gate voltage drops below 2.0 V (typ.) referred to VEE2, to be connected directly to the IGBT gate with 3.0 A typical clamp peak current.
7	OUT	output	Combined source and sink output to the external IGBT switching between VCC2 and VEE2 (10.0 A typ. source, 9.0 A typ. sink), controlled by IN+ and IN- and held low by active shut down during UVLO.
8	VCC2	power_in	Positive power supply of the output driving circuit, 10 V to 35 V operating (40 V absolute maximum) referred to VEE2, requiring a blocking capacitor placed close to the pin.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	SOIC-8-300mil
Category	Power Management
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
UVLO threshold input side (on)	VUVLOH1			3.1	V		13
UVLO threshold input side (off)	VUVLOL1	2.5			V		13
UVLO hysteresis input side	VHYS1	0.1	0.2		V		13
UVLO threshold output side (on)	VUVLOH2,1			10	V	1ED3120MU12H, 1ED3122MU12H, 1ED3123MU12H	13
UVLO threshold output side (off)	VUVLOL2,1	8			V	1ED3120MU12H, 1ED3122MU12H, 1ED3123MU12H	13
UVLO hysteresis output side	VHYS2	0.8			V		13
Quiescent current input side	IQ1			1.1	mA	static, output low	13
Quiescent current output side	IQ2			2	mA		13
Start up time	tSTART		2.5	20	µs		13
UVLO detection filter time	tUVLOflt	50			ns		13
IN+, IN- low input threshold voltage	VIN,L			1.1	V		13
IN+, IN- high input threshold voltage	VIN,H	2.5			V		13
IN+, IN- low/high hysteresis	VIN,HYS	0.5	0.8		V		13
IN+, IN- input current	IIN			100	µA	VVCC1 = 5 V; VIN ≤ VVCC1	13
IN+ pull down resistor	RIN,PD		75		kΩ		13
IN- pull up resistor	RIN,PU		75		kΩ		13
High level output peak current	IOUT,H	4	10		A	VCC2-OUT = 15 V, Output on	14
High level output on resistance	RDSON,H	0.3	0.55	0.85	Ω	IOUT,H = 0.1 A	14
Low level output peak current	IOUT,L	4	9		A	OUT-VEE2 = 15 V, Output off	14
Low level output on resistance	RDSON,L	0.3	0.45	0.65	Ω	IOUT,L = 0.1 A	14
Low level clamp peak current	ICLAMP,L	2	3		A	VCLAMP = 2.0 V	14
Low level clamp on resistance	RDSON,CLP	0.33	0.55	0.76	Ω	ICLAMP,L = 0.1 A	14
CLAMP threshold voltage	VCLAMP	1.6	2	2.4	V	CLAMP-VEE2	14
CLAMP comparator to CLAMP activation delay time	tCLPDLY			80	ns	VCLAMP ≤ 2.0 V	14
High level output voltage	ΔVOUT,H			0.3	V	VCC2-VOUT,H; IOUT = 20 mA	14
Low level output voltage	ΔVOUT,L			0.1	V	VCC2-VOUT,H; IOUT = 20 mA	14
Short circuit clamp voltage between OUT+/CLAMP and VCC2	VCLP			2	V	Output on, IOUT = 500 mA, t < 10 µs	14
Input to output propagation delay ON	tPDON	80	90	100	ns	CLOAD = 100 pF, IN turn-on threshold to 10% output on	15
Input to output propagation delay OFF	tPDOFF	80	90	100	ns	CLOAD = 100 pF, IN turn-off threshold to 90% output off	15
Input to output propagation delay distortion	tPDISTO	-5	0	5	ns	tPDOFF - tPDON	16
Input pulse suppression time (filter time)	tINFLT	30			ns	shorter pulses will not propagate to the output	16
Minimum input pulse length	tMININ			40	ns		16
Input to output propagation delay variation due to temperature	tPD,T			14	ns		16
Input to output propagation delay distortion variation due to temperature	tPDISTO,T			3	ns		16
Input to output, part to part propagation delay ON variation	/tPDon,P2P/			7	ns	CLOAD = 100 pF	16
Rise time	tRISE			15	ns	CLOAD = 100 pF	16
Fall time	tFALL			15	ns	CLOAD = 100 pF	16
Rise time	tRISE			30	ns	CLOAD = 1 nF	16
Fall time	tFALL			30	ns	CLOAD = 1 nF	16
Active shut down voltage, cold	VACTSD,C			1.9	V	IOUT = 10 mA; VCC2 unsupplied; TA < 20°C	16
Active shut down voltage, hot	VACTSD,H			1.7	V	IOUT- = 10 mA; VCC2 unsupplied; TA ≥ 20°C	16
Power supply output side	VVCC2	10		35	V	With respect to VEE2	12
Power supply input side	VVCC1	3.1		15	V		12
Logic input voltages (IN+, IN-)	VIN	-0.3		5.5	V		12
Switching frequency	fSW			1	MHz	max PD applies	12
Ambient temperature	TA	-40		125	°C		12
Common mode transient immunity	CMTI	-200		200	kV/µs	VOFFSET,test = 1500 V	12
Input to output offset voltage	VOFFSET			2300	V	VVEE2,max-VVEE2,min with VVEE2,max ≥ VGND1 ≥ VVEE2,min	11
Power supply output side	VVCC2	-0.3		40	V	With respect to VEE2	11
Gate driver output (OUT+, OUT-, OUT, CLAMP)	VOUT	-0.3		0.3	V	VEE2 - 0.3 to VCC2 + 0.3, with respect to VEE2	11
Power supply input side	VVCC1	-0.3		17	V	VCC1 - GND1	11
Logic input voltages (IN+, IN-)	VIN	-0.3		6.5	V	IN - GND1	11
Junction temperature	TJ	-40		150	°C		11
Storage temperature	TStg	-55		150	°C		11
Power dissipation (input side)	PD,IN			100	mW	TA = 65°C	11
Power dissipation (output side)	PD,OUT			700	mW	TA = 65°C	11
ESD robustness HBM	VESD,HBM			4	kV	Human body model	11
Thermal resistance junction to ambient	RthJA,OUT			88	K/W	TA = 85°C 300 mil, 1s0p, PJ = 266 mW	11
Characterization parameter junction to package top input side	ΨJtop			6	K/W		11

CAD (KiCad official)

Symbol: 1ED3122MU12HXUMA1
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8-300mil (KiCad packages3D, STEP)
3D model files: 1ed3122mu12hxuma1-etched.step / 1ed3122mu12hxuma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 1ed3122mu12hxuma1.step / 1ed3122mu12hxuma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (20 pp, sha256 dbbdbb24e964046a, retrieved 2026-10-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# 1ED3122MU12HXUMA1

**Infineon Technologies** · Gate Drive ICs · SOIC-8-300mil

1ED3122MU12HXUMA1 from Infineon Technologies, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC1 | power_in | Positive logic supply for the input side with a 3.3 V up to 15 V wide operating range (3.1 V to 15 V operating, 17 V absolute maximum, referred to GND1). |
| 2 | IN+ | input | Non-inverted driver input (active high) with internal noise filter and weak 75 kΩ pull-down favoring off-state; absolute maximum 6.5 V referred to GND1. |
| 3 | IN- | input | Inverted driver input (active low) with internal noise filter and weak 75 kΩ pull-up favoring off-state; absolute maximum 6.5 V referred to GND1. |
| 4 | GND1 | power_in | Ground connection of the input circuit (logic ground) to which input-side parameters are referred. |
| 5 | VEE2 | power_in | Reference ground of the output driving circuit, connected to the negative supply in case of a bipolar supply. |
| 6 | CLAMP | output | Active Miller clamp output that ties to VEE2 during off-state once gate voltage drops below 2.0 V (typ.) referred to VEE2, to be connected directly to the IGBT gate with 3.0 A typical clamp peak current. |
| 7 | OUT | output | Combined source and sink output to the external IGBT switching between VCC2 and VEE2 (10.0 A typ. source, 9.0 A typ. sink), controlled by IN+ and IN- and held low by active shut down during UVLO. |
| 8 | VCC2 | power_in | Positive power supply of the output driving circuit, 10 V to 35 V operating (40 V absolute maximum) referred to VEE2, requiring a blocking capacitor placed close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8-300mil |
| Category | Power Management |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| UVLO threshold input side (on) | VUVLOH1 |  |  | 3.1 | V |  | 13 |
| UVLO threshold input side (off) | VUVLOL1 | 2.5 |  |  | V |  | 13 |
| UVLO hysteresis input side | VHYS1 | 0.1 | 0.2 |  | V |  | 13 |
| UVLO threshold output side (on) | VUVLOH2,1 |  |  | 10 | V | 1ED3120MU12H, 1ED3122MU12H, 1ED3123MU12H | 13 |
| UVLO threshold output side (off) | VUVLOL2,1 | 8 |  |  | V | 1ED3120MU12H, 1ED3122MU12H, 1ED3123MU12H | 13 |
| UVLO hysteresis output side | VHYS2 | 0.8 |  |  | V |  | 13 |
| Quiescent current input side | IQ1 |  |  | 1.1 | mA | static, output low | 13 |
| Quiescent current output side | IQ2 |  |  | 2 | mA |  | 13 |
| Start up time | tSTART |  | 2.5 | 20 | µs |  | 13 |
| UVLO detection filter time | tUVLOflt | 50 |  |  | ns |  | 13 |
| IN+, IN- low input threshold voltage | VIN,L |  |  | 1.1 | V |  | 13 |
| IN+, IN- high input threshold voltage | VIN,H | 2.5 |  |  | V |  | 13 |
| IN+, IN- low/high hysteresis | VIN,HYS | 0.5 | 0.8 |  | V |  | 13 |
| IN+, IN- input current | IIN |  |  | 100 | µA | VVCC1 = 5 V; VIN ≤ VVCC1 | 13 |
| IN+ pull down resistor | RIN,PD |  | 75 |  | kΩ |  | 13 |
| IN- pull up resistor | RIN,PU |  | 75 |  | kΩ |  | 13 |
| High level output peak current | IOUT,H | 4 | 10 |  | A | VCC2-OUT = 15 V, Output on | 14 |
| High level output on resistance | RDSON,H | 0.3 | 0.55 | 0.85 | Ω | IOUT,H = 0.1 A | 14 |
| Low level output peak current | IOUT,L | 4 | 9 |  | A | OUT-VEE2 = 15 V, Output off | 14 |
| Low level output on resistance | RDSON,L | 0.3 | 0.45 | 0.65 | Ω | IOUT,L = 0.1 A | 14 |
| Low level clamp peak current | ICLAMP,L | 2 | 3 |  | A | VCLAMP = 2.0 V | 14 |
| Low level clamp on resistance | RDSON,CLP | 0.33 | 0.55 | 0.76 | Ω | ICLAMP,L = 0.1 A | 14 |
| CLAMP threshold voltage | VCLAMP | 1.6 | 2 | 2.4 | V | CLAMP-VEE2 | 14 |
| CLAMP comparator to CLAMP activation delay time | tCLPDLY |  |  | 80 | ns | VCLAMP ≤ 2.0 V | 14 |
| High level output voltage | ΔVOUT,H |  |  | 0.3 | V | VCC2-VOUT,H; IOUT = 20 mA | 14 |
| Low level output voltage | ΔVOUT,L |  |  | 0.1 | V | VCC2-VOUT,H; IOUT = 20 mA | 14 |
| Short circuit clamp voltage between OUT+/CLAMP and VCC2 | VCLP |  |  | 2 | V | Output on, IOUT = 500 mA, t < 10 µs | 14 |
| Input to output propagation delay ON | tPDON | 80 | 90 | 100 | ns | CLOAD = 100 pF, IN turn-on threshold to 10% output on | 15 |
| Input to output propagation delay OFF | tPDOFF | 80 | 90 | 100 | ns | CLOAD = 100 pF, IN turn-off threshold to 90% output off | 15 |
| Input to output propagation delay distortion | tPDISTO | -5 | 0 | 5 | ns | tPDOFF - tPDON | 16 |
| Input pulse suppression time (filter time) | tINFLT | 30 |  |  | ns | shorter pulses will not propagate to the output | 16 |
| Minimum input pulse length | tMININ |  |  | 40 | ns |  | 16 |
| Input to output propagation delay variation due to temperature | tPD,T |  |  | 14 | ns |  | 16 |
| Input to output propagation delay distortion variation due to temperature | tPDISTO,T |  |  | 3 | ns |  | 16 |
| Input to output, part to part propagation delay ON variation | /tPDon,P2P/ |  |  | 7 | ns | CLOAD = 100 pF | 16 |
| Rise time | tRISE |  |  | 15 | ns | CLOAD = 100 pF | 16 |
| Fall time | tFALL |  |  | 15 | ns | CLOAD = 100 pF | 16 |
| Rise time | tRISE |  |  | 30 | ns | CLOAD = 1 nF | 16 |
| Fall time | tFALL |  |  | 30 | ns | CLOAD = 1 nF | 16 |
| Active shut down voltage, cold | VACTSD,C |  |  | 1.9 | V | IOUT = 10 mA; VCC2 unsupplied; TA < 20°C | 16 |
| Active shut down voltage, hot | VACTSD,H |  |  | 1.7 | V | IOUT- = 10 mA; VCC2 unsupplied; TA ≥ 20°C | 16 |
| Power supply output side | VVCC2 | 10 |  | 35 | V | With respect to VEE2 | 12 |
| Power supply input side | VVCC1 | 3.1 |  | 15 | V |  | 12 |
| Logic input voltages (IN+, IN-) | VIN | -0.3 |  | 5.5 | V |  | 12 |
| Switching frequency | fSW |  |  | 1 | MHz | max PD applies | 12 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 12 |
| Common mode transient immunity | CMTI | -200 |  | 200 | kV/µs | VOFFSET,test = 1500 V | 12 |
| Input to output offset voltage | VOFFSET |  |  | 2300 | V | VVEE2,max-VVEE2,min with VVEE2,max ≥ VGND1 ≥ VVEE2,min | 11 |
| Power supply output side | VVCC2 | -0.3 |  | 40 | V | With respect to VEE2 | 11 |
| Gate driver output (OUT+, OUT-, OUT, CLAMP) | VOUT | -0.3 |  | 0.3 | V | VEE2 - 0.3 to VCC2 + 0.3, with respect to VEE2 | 11 |
| Power supply input side | VVCC1 | -0.3 |  | 17 | V | VCC1 - GND1 | 11 |
| Logic input voltages (IN+, IN-) | VIN | -0.3 |  | 6.5 | V | IN - GND1 | 11 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 11 |
| Storage temperature | TStg | -55 |  | 150 | °C |  | 11 |
| Power dissipation (input side) | PD,IN |  |  | 100 | mW | TA = 65°C | 11 |
| Power dissipation (output side) | PD,OUT |  |  | 700 | mW | TA = 65°C | 11 |
| ESD robustness HBM | VESD,HBM |  |  | 4 | kV | Human body model | 11 |
| Thermal resistance junction to ambient | RthJA,OUT |  |  | 88 | K/W | TA = 85°C 300 mil, 1s0p, PJ = 266 mW | 11 |
| Characterization parameter junction to package top input side | ΨJtop |  |  | 6 | K/W |  | 11 |

## CAD (KiCad official)

- Symbol: `1ED3122MU12HXUMA1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8-300mil (KiCad packages3D, STEP)
- 3D model files: `1ed3122mu12hxuma1-etched.step` / `1ed3122mu12hxuma1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `1ed3122mu12hxuma1.step` / `1ed3122mu12hxuma1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/1ed3122mu12hxuma1-datasheet.pdf) (20 pp, sha256 `dbbdbb24e964046a`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/1ed3122mu12hxuma1-datasheet.pdf)