component
π161M31
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 6d ago |
| viewers | 6d ago |
| 161m31-etched.glb | 6d ago |
| 161m31-etched.step | 6d ago |
| 161m31-hero.glb | 6d ago |
| 161m31-hero.overlay.json | 6d ago |
| 161m31.glb | 6d ago |
| 161m31.kicad_mod | 6d ago |
| 161m31.kicad_sym | 6d ago |
| 161m31.lbr | 6d ago |
| 161m31.step | 6d ago |
| package.json | 6d ago |
| page.json | 6d ago |
| README.md | 6d ago |
π161M31
2Pai Semi · Digital Isolators · SOIC-16
π161M31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1 (3.0 V to 5.5 V operating range, referenced to GND1). |
| 2 | VIA | input | Logic input A on side 1. |
| 3 | VIB | input | Logic input B on side 1. |
| 4 | VIC | input | Logic input C on side 1. |
| 5 | VID | input | Logic input D on side 1. |
| 6 | VIE | input | Logic input E on side 1. |
| 7 | VOF | output | Logic output F on side 1 (reverse channel, driven from the VIF input on side 2). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | VIF | input | Logic input F on side 2. |
| 11 | VOE | output | Logic output E on side 2. |
| 12 | VOD | output | Logic output D on side 2. |
| 13 | VOC | output | Logic output C on side 2. |
| 14 | VOB | output | Logic output B on side 2. |
| 15 | VOA | output | Logic output A on side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2 (3.0 V to 5.5 V operating range, referenced to GND2). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Data Rate | 0 | 10 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltages | VDD1-GND1, VDD2-GND2 | -0.5 | 7 | V | TA = 25°C | 4 | |
| Average Output Current per Pin | IO1, IO2 | -10 | 10 | mA | Side 1 / Side 2 output current | 4 | |
| Common-Mode Transients Immunity | -200 | 200 | kV/µs | 4 | |||
| Storage Temperature | TST | -65 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Propagation Delay Time | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 5VDC supply | 5 |
| Propagation Delay Time | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0.3 | 3 | ns | / tpHL - tpLH / @ 5VDC supply | 5 | |
| Pulse Width Distortion | PWD | 0.4 | 3 | ns | / tpHL - tpLH / @ 3.3VDC supply | 5 | |
| Part to Part Propagation Delay Skew | tPSK | 2 | ns | same temperature, load and voltage @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 1.8 | ns | between any two output channels in single device @ 5VDC supply | 5 | |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 2 | ns | between any two output channels in single device @ 3.3VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | See Figure 11. | 5 | ||
| Minimum Pulse Width | PW | 100 | ns | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 10 | Mbps | Within PWD limit | 5 | |||
| Common-Mode Transient Immunity | CMTI | 75 | kV/µs | VIN = VDDx or 0V, VCM = 1000 V | 5 | ||
| ESD (HBM) | ESD | 8 | kV | Human body model, ±8 kV | 5 | ||
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 6 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDx | 6 |
| VDDx Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.75 | 2.95 | V | 6 | |
| VDDx Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.6 | 2.75 | V | 7 | |
| VDDx Hysteresis | VDDxUVH | 0.15 | V | 7 | |||
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.55 | 0.68 | 0.89 | mA | 5VDC, VI=0V for π16xMx0, CL = 0 pF | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 1.98 | 2.48 | 3.22 | mA | 5VDC, VI=5V for π16xMx1, CL = 0 pF | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.75 | 0.94 | 1.22 | mA | 5VDC, VI=5V for π16xMx0, CL = 0 pF | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 1.91 | 2.39 | 3.11 | mA | 5VDC, VI=0V for π16xMx1, CL = 0 pF | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.54 | 0.68 | 0.88 | mA | 3.3VDC, VI=0V for π16xMx0, CL = 0 pF | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 1.96 | 2.45 | 3.18 | mA | 3.3VDC, VI=3.3V for π16xMx1, CL = 0 pF | 7 |
| Quiescent Supply Current Side 1 | IDD1 (Q) | 0.64 | 0.8 | 1.04 | mA | 3.3VDC, VI=3.3V for π16xMx0, CL = 0 pF | 7 |
| Quiescent Supply Current Side 2 | IDD2 (Q) | 1.83 | 2.28 | 2.97 | mA | 3.3VDC, VI=0V for π16xMx1, CL = 0 pF | 7 |
| Dynamic Input Supply Current per Channel | IDDI (D) | 9 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 38 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Input Supply Current per Channel | IDDI (D) | 5 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 23 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Jitter (peak-to-peak) | 120 | ps p-p | See the Jitter Measurement section | 5 | |||
| Jitter (rms) | 20 | ps rms | See the Jitter Measurement section | 5 | |||
| IC Junction to Ambient Thermal Resistance | θJA | 76 | °C/W | Thermocouple located at center of package underside | 9 | ||
| Rated Dielectric Insulation Voltage | 3000 | V rms | 1-minute duration | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-11, eachπ160M3x/π161M3x/π162M3x /π163M3x is proof tested by applying an insulation test voltage ≥ 848 V peak for 1 sec (partial discharge detection limit = 5 pC); e | 10 |
CAD (KiCad official)
- Symbol:
π161M31 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
161m31-etched.step/161m31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);161m31.step/161m31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (19 pp, sha256
5bda2a660ddaeeda, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).