component
π142M31
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2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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π142M31
2Pai Semi · Digital Isolators · SOIC-16
π142M31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified for 3.0 V to 5.5 V operation. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A on side 1, transmitted across the isolation barrier to output VOA; it must be held low while VDD1 is unpowered to avoid back-powering VDD1 through its ESD protection. |
| 4 | VIB | input | Logic input B on side 1, transmitted across the isolation barrier to output VOB; it must be held low while VDD1 is unpowered to avoid back-powering VDD1 through its ESD protection. |
| 5 | VOC | output | Logic output C on side 1, a reverse-direction channel that follows input VIC (pin 12) from side 2. |
| 6 | VOD | output | Logic output D on side 1, a reverse-direction channel that follows input VID (pin 11) from side 2. |
| 7 | NC | unconnected | No connect for π142M3x; this pin is EN1 (output enable, active when high or open) only on the π142M6x variant. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC | unconnected | No connect for π142M3x; this pin is EN2 (output enable, active when high or open) only on the π142M6x variant. |
| 11 | VID | input | Logic input D on side 2, a reverse-direction channel that drives output VOD (pin 6). |
| 12 | VIC | input | Logic input C on side 2, a reverse-direction channel that drives output VOC (pin 5). |
| 13 | VOB | output | Logic output B on side 2, follows input VIB (pin 4) across the isolation barrier. |
| 14 | VOA | output | Logic output A on side 2, follows input VIA (pin 3) across the isolation barrier. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified for 3.0 V to 5.5 V operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| Low Level Input Signal Voltage | VIL | 0 | V | 4 | |||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Maximum Data Rate | 0 | 10 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | 3 | |||
| Input Voltages (VIA, VIB) | -0.5 | V | Upper limit is VDDx + 0.5 V as printed | 3 | |||
| Output Voltages (VOA, VOB) | -0.5 | V | Upper limit is VDDx + 0.5 V as printed | 3 | |||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 3 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 3 | ||
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | 3 | |||
| Storage Temperature Range | TST | -65 | 150 | °C | 3 | ||
| Minimum Pulse Width | PW | 100 | ns | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 10 | Mbps | Within PWD limit | 5 | |||
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 50% input to 50% output signal, @ 5VDC supply | 5 |
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 50% input to 50% output signal, @ 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0 | 0.3 | 0.8 | ns | /tpHL - tpLH/, @ 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | 1 | ns | Between any two devices, @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 1 | ns | Between output channels in one device, @ 5VDC supply | 5 | |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 0.8 | ns | Between output channels in one device, @ 3.3VDC supply | 5 | |
| ESD Human Body Model | ESD | -8 | 8 | kV | HBM, all pins | 5 | |
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 6 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 838 | 1048 | 1362 | µA | @ 5VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 838 | 1048 | 1362 | µA | @ 5VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 872 | 1090 | 1417 | µA | @ 5VDC supply, 5V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 872 | 1090 | 1417 | µA | @ 5VDC supply, 5V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 829 | 1036 | 1347 | µA | @ 3.3VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 829 | 1036 | 1347 | µA | @ 3.3VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 816 | 1020 | 1326 | µA | @ 3.3VDC supply, 3.3V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 816 | 1020 | 1326 | µA | @ 3.3VDC supply, 3.3V input signal | 6 |
| Supply Current vs Throughput, 150 kbps | IDD1 | 1.08 | 1.62 | mA | CL = 0 pF, @ 5VDC supply | 7 | |
| Supply Current vs Throughput, 1 Mbps | IDD1 | 1.16 | 1.74 | mA | CL = 0 pF, @ 5VDC supply | 7 | |
| Supply Current vs Throughput, 10 Mbps | IDD1 | 1.94 | 2.91 | mA | CL = 0 pF, @ 5VDC supply | 7 | |
| Supply Current vs Throughput, 150 kbps | IDD1 | 1.04 | 1.56 | mA | CL = 0 pF, @ 3.3VDC supply | 7 | |
| Supply Current vs Throughput, 1 Mbps | IDD1 | 1.08 | 1.62 | mA | CL = 0 pF, @ 3.3VDC supply | 7 | |
| Supply Current vs Throughput, 10 Mbps | IDD1 | 1.54 | 2.31 | mA | CL = 0 pF, @ 3.3VDC supply | 7 | |
| Dynamic Input Supply Current per Channel | IDDI (D) | 9 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 5VDC supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 38 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 5VDC supply | 5 | ||
| Dynamic Input Supply Current per Channel | IDDI (D) | 5 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 3.3VDC supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 23 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 3.3VDC supply | 5 | ||
| Common-Mode Transient Immunity | CMTI | 75 | kV/µs | VIN = VDDx2 or 0V, VCM = 1000 V | 5 | ||
| VDDx1 Hysteresis | VDDxUVH | 0.15 | V | 6 | |||
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90%, signal terminated 50Ω | 5 | ||
| IC Junction to Ambient Thermal Resistance | θJA | 100 | °C/W | Thermocouple at center of package underside; π14xM3x column | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 | 8 |
CAD (KiCad official)
- Symbol:
π142M31 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
142m31-etched.step/142m31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);142m31.step/142m31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (17 pp, sha256
705f6f25144df2ab, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# π142M31
**2Pai Semi** · Digital Isolators · SOIC-16
π142M31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified for 3.0 V to 5.5 V operation. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A on side 1, transmitted across the isolation barrier to output VOA; it must be held low while VDD1 is unpowered to avoid back-powering VDD1 through its ESD protection. |
| 4 | VIB | input | Logic input B on side 1, transmitted across the isolation barrier to output VOB; it must be held low while VDD1 is unpowered to avoid back-powering VDD1 through its ESD protection. |
| 5 | VOC | output | Logic output C on side 1, a reverse-direction channel that follows input VIC (pin 12) from side 2. |
| 6 | VOD | output | Logic output D on side 1, a reverse-direction channel that follows input VID (pin 11) from side 2. |
| 7 | NC | unconnected | No connect for π142M3x; this pin is EN1 (output enable, active when high or open) only on the π142M6x variant. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC | unconnected | No connect for π142M3x; this pin is EN2 (output enable, active when high or open) only on the π142M6x variant. |
| 11 | VID | input | Logic input D on side 2, a reverse-direction channel that drives output VOD (pin 6). |
| 12 | VIC | input | Logic input C on side 2, a reverse-direction channel that drives output VOC (pin 5). |
| 13 | VOB | output | Logic output B on side 2, follows input VIB (pin 4) across the isolation barrier. |
| 14 | VOA | output | Logic output A on side 2, follows input VIA (pin 3) across the isolation barrier. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified for 3.0 V to 5.5 V operation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | 3 | | 5.5 | V | | 4 |
| Low Level Input Signal Voltage | VIL | 0 | | | V | | 4 |
| High Level Output Current | IOH | -6 | | | mA | | 4 |
| Low Level Output Current | IOL | | | 6 | mA | | 4 |
| Maximum Data Rate | | 0 | | 10 | Mbps | | 4 |
| Junction Temperature | TJ | -40 | | 150 | °C | | 4 |
| Ambient Operating Temperature | TA | -40 | | 125 | °C | | 4 |
| Supply Voltages (VDD1-GND1, VDD2-GND2) | | -0.5 | | 7 | V | | 3 |
| Input Voltages (VIA, VIB) | | -0.5 | | | V | Upper limit is VDDx + 0.5 V as printed | 3 |
| Output Voltages (VOA, VOB) | | -0.5 | | | V | Upper limit is VDDx + 0.5 V as printed | 3 |
| Average Output Current per Pin, Side 1 | IO1 | -10 | | 10 | mA | | 3 |
| Average Output Current per Pin, Side 2 | IO2 | -10 | | 10 | mA | | 3 |
| Common-Mode Transients Immunity | | -150 | | 150 | kV/µs | | 3 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 3 |
| Minimum Pulse Width | PW | 100 | | | ns | Within pulse width distortion (PWD) limit | 5 |
| Maximum Data Rate | | | | 10 | Mbps | Within PWD limit | 5 |
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 50% input to 50% output signal, @ 5VDC supply | 5 |
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | 50% input to 50% output signal, @ 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0 | 0.3 | 0.8 | ns | /tpHL - tpLH/, @ 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | | | 1 | ns | Between any two devices, @ 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | | 1 | ns | Between output channels in one device, @ 5VDC supply | 5 |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | | 0.8 | ns | Between output channels in one device, @ 3.3VDC supply | 5 |
| ESD Human Body Model | ESD | -8 | | 8 | kV | HBM, all pins | 5 |
| Low Level Output Voltage | VOL | 0 | | 0.1 | V | 20 µA output current | 6 |
| Low Level Output Voltage | VOL | 0.1 | | 0.2 | V | 2 mA output current | 6 |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | | 6 |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 838 | 1048 | 1362 | µA | @ 5VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 838 | 1048 | 1362 | µA | @ 5VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 872 | 1090 | 1417 | µA | @ 5VDC supply, 5V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 872 | 1090 | 1417 | µA | @ 5VDC supply, 5V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 829 | 1036 | 1347 | µA | @ 3.3VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 829 | 1036 | 1347 | µA | @ 3.3VDC supply, 0V input signal | 6 |
| Quiescent Supply Current IDD1 (Q) | IDD1 (Q) | 816 | 1020 | 1326 | µA | @ 3.3VDC supply, 3.3V input signal | 6 |
| Quiescent Supply Current IDD2 (Q) | IDD2 (Q) | 816 | 1020 | 1326 | µA | @ 3.3VDC supply, 3.3V input signal | 6 |
| Supply Current vs Throughput, 150 kbps | IDD1 | | 1.08 | 1.62 | mA | CL = 0 pF, @ 5VDC supply | 7 |
| Supply Current vs Throughput, 1 Mbps | IDD1 | | 1.16 | 1.74 | mA | CL = 0 pF, @ 5VDC supply | 7 |
| Supply Current vs Throughput, 10 Mbps | IDD1 | | 1.94 | 2.91 | mA | CL = 0 pF, @ 5VDC supply | 7 |
| Supply Current vs Throughput, 150 kbps | IDD1 | | 1.04 | 1.56 | mA | CL = 0 pF, @ 3.3VDC supply | 7 |
| Supply Current vs Throughput, 1 Mbps | IDD1 | | 1.08 | 1.62 | mA | CL = 0 pF, @ 3.3VDC supply | 7 |
| Supply Current vs Throughput, 10 Mbps | IDD1 | | 1.54 | 2.31 | mA | CL = 0 pF, @ 3.3VDC supply | 7 |
| Dynamic Input Supply Current per Channel | IDDI (D) | | 9 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 5VDC supply | 5 |
| Dynamic Output Supply Current per Channel | IDDO (D) | | 38 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 5VDC supply | 5 |
| Dynamic Input Supply Current per Channel | IDDI (D) | | 5 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 3.3VDC supply | 5 |
| Dynamic Output Supply Current per Channel | IDDO (D) | | 23 | | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF, @ 3.3VDC supply | 5 |
| Common-Mode Transient Immunity | CMTI | | 75 | | kV/µs | VIN = VDDx2 or 0V, VCM = 1000 V | 5 |
| VDDx1 Hysteresis | VDDxUVH | | 0.15 | | V | | 6 |
| Output Signal Rise/Fall Time | tr/tf | | 1.5 | | ns | 10% to 90%, signal terminated 50Ω | 5 |
| IC Junction to Ambient Thermal Resistance | θJA | | 100 | | °C/W | Thermocouple at center of package underside; π14xM3x column | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | In accordance with DIN V VDE V 0884-10, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 | 8 |
## CAD (KiCad official)
- Symbol: `π142M31`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `142m31-etched.step` / `142m31-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `142m31.step` / `142m31.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [2Pai Semi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885176819077120) (17 pp, sha256 `705f6f25144df2ab`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/142m31-datasheet.pdf)